This paper is a review of methods and techniques used for precise measurement of time intervals (TIs) or precise conversion of TIs to digital data. The following methods are described: the counter method and averaging, time stretching, time-to-amplitude conversion followed by analogue-to-digital conversion, the Vernier method, conversion utilizing tapped delay lines, and interpolation methods. ...

This paper presents a digitally programmable delay line intended for use as timing generator in a RADAR ranging system. Traditional delay lines are realized selecting the delayed signal from a tap in a cascade of delay elements, resulting in a delay resolution limited by the matching errors between the delay elements. The architecture of the programmable delay line presented in this paper uses ...

This paper presents an ultra-wide-range all-digital delaylocked loop (DLL). The proposed DLL uses a novel delay circuit which uses the transistor’s leakage current in advanced CMOS process to generate a very large propagation delay. Thus, the proposed DLL can operate at very low frequency with small chip area and low power consumption. The proposed DLL can operate from 600 kHz to 1.2GHz in the ...

the aim of this paper is to minimize output phase noise for the pure signal synthesis in the frequency synthesizers. for this purpose, first, an exact mathematical model of phase locked loop (pll) based frequency synthesizer is described and analyzed. then, an exact closed-form formula in terms of synthesizer bandwidth and total output phase noise is extracted. based on this formula, the phase ...

This paper describes a dual-loop delay-locked loop (DLL) which overcomes the problem of a limited delay range by using multiple voltage-controlled delay lines (VCDLs). A reference loop generates quadrature clocks, which are then delayed with controllable amounts by four VCDLs and multiplexed to generate the output clock in a main loop. This architecture enables the DLL to emulate the infinite-l...

Since very short pulse waves are transmitted, UWB systems have excellent accuracy in terms of distance measurement. In order to measure the distance between the terminals, the transmitted pulses have to be synchronized by a delay-lock-loop (DLL) in the receiver. In this paper the performance of the DLL is evaluated. Its performance depends the timing jitter between the local clocks of the termi...

This paper describes a dual delay-locked loop architecture which achieves low jitter, unlimited (modulo 2 ) phase shift, and large operating range. The architecture employs a core loop to generate coarsely spaced clocks, which are then used by a peripheral loop to generate the main system clock through phase interpolation. The design of an experimental prototype in a 0.8m CMOS technology is des...

This paper describes a 1.6GHz clock synthesizer which employs a delay locked loop (DLL) to generate multiple phases that are combined to produce the desired output clock frequency. A self correcting circuit ensures that the DLL arrives at the correct locked state irrespective of its power-up state or following either a wide variation in the input reference clock frequency or missing pulses in t...

This paper describes a low-voltage, low-jitter clock synthesizer and a temperaturecompensated tunable oscillator. Both of these circuits employ a self-correcting Delay-Locked Loop (DLL) which solves the problem of false locking associated with conventional DLLs. This DLL does not require the delay control voltage to be set on power-up, it can recover from missing reference clock pulses and beca...

This paper describes a 1.6GHz clock synthesizer which employs a delay locked loop (DLL) to generate multiple phases that are combined to produce the desired output clock frequency. A self correcting circuit ensures that the DLL arrives at the correct locked state irrespective of its power-up state or following either a wide variation in the input reference clock frequency or missing pulses in t...