Recently most of integrated circuit chips are made from monolithic IC, which can be manufactured at low cost. In monolithic IC, absolute error which is proportion of the difference of actual value to the designed value of each element is large (several tens of percentages), but the maximum difference of the absolute error of devices on a chip, is small (a few percentages). So it is suitable to ...

Unlike analog calibration, digital calibration alone does not correct or create analog decision levels. Therefore, the uncalibrated ADC must provide decision levels spaced no greater than lLSB at the intended resolution. In lb/stage pipeline ADCs with nominal gain of 2, missing decision levels result when the input of any stage exceeds full scale due to capacitor mismatch, capacitor non-lineari...

In order to improve both resolution and stability of single bit high order Sigma-Delta Modulators, quantization noise suppression should be carried out not only at DC but also within the bandwidth of interest. This noise suppression at frequencies different from zero is carried out with the use of resonators. Switched-Capacitor resonators at fS/n can be designed using integrating or delaying el...

The capacitor has become the dominant passive component for analog circuits designed in standard CMOS processes. Thus, capacitor matching is a primary factor in determining the precision of many analog circuit techniques. In this paper, we present experimental measurements of the mismatch between square capacitors ranging in size from 6 pm x 6 pm to 20 pm x 20 pm fabricated in a standard 2 pm d...

This paper describes a technique for digital error correction in pipelined analog-digital converters. It makes use of a slow, high resolution ADC in conjunction with an LMS algorithm to perform error correction in the background during normal conversion. The algorithm will be shown to correct for errors due to capacitor ratio mismatch, finite amplifier gain and charge injection within the same ...

This paper describes a background calibration method for enhancing the accuracy and linearity of a switched-capacitor digital-to-analog converter. It can be used alone or in combination with mismatch shaping to achieve very high accuracy and linearity combined with high speed.

This paper describes a suitable mathematical model for the design of high-speed, high-resolution pipeline ADCs. The effect of capacitor mismatch and finite amplifier bandwidth and gain on the converter INL and DNL are accurately modelled. On the basis of this model a design optimisation method is provided. 2005 Elsevier Ltd. All rights reserved.

We overcome mismatch constraints of capacitor DAC design in SAR ADCs using a completely reconfigurable DAC with content addressable memory beneath groupings of unit capacitors. We demonstrate a linearity optimization technique in simulation and measurement. We achieve a nearly 2-bit repeatable ENOB improvement with a peak of 11.3 bits.

A digital calibration technique for high resolution SAR ADC with only one redundant conversion bit is presented in this paper. The proposed work employs no extra calibration DAC or input signal as calibration reference. Calibration signal is generated through switching redistribution DAC in two calibration phase, so that calibration accuracy will not be affected by input signal distribution. DA...

SAR-ADC is best suited for low power applications where power has a trade-off with speed. Use of redundant circuitry reduces the on chip area making it cost effective. DAC is one of the components of SAR-ADC that introduces error voltage due to mismatch and consumes large power other than comparator. Low power DAC architectures have been studied and analysed. To account for capacitor mismatch i...