An AES algorithm is implemented on FPGA platform to improve the safety of data in transmission. AES algorithms can be implemented on FPGA in order to speed data processing and reduce time for key generating. We achieve higher performance by maintaining standard speed and reliability with low area and power. The 128 bit AES algorithm is implements on a FPGA using VHDL language with help of Xilin...

Presents the design of variable array multipliers using VHDL. Multipliers of various operand sizes for different target processes can be implemented using the proposed VHDL based approach. The multipliers will be testable with a constant number of test vectors irrespective of the operand word lengths. A fast test pattern generator is also developed for simulation of the multiplier designs and s...

This article describes a prototype implementation of a symbolic model checker for a subset of VHDL. The model checker applies a number of techniques to reduce the search space, thus allowing for efficient verification of real circuits. We have completed an initial release of the VHDL model checker and have used it to verify complex circuits, including the control logic of a commercial RISC micr...

The requirements of large system design place great demands upon the per formance and d iagnost ic capabilities of simulation. This paper explains how these requirements have been satisfied by an internallydeveloped simulator using a proprietary language and a proprietary platform. More significantly, this paper describes how the strengths of that system have been developed to create a VHDL sim...

The use of standard languages like VHDL and C for the description of hardware and software IP has became a common practice. Despite this, these languages, specially the hardware description languages lack constructs that allow the IP designer to develop highly re-usable IP blocks. In this paper is described an abstract communication mechanism that uses extensions to the VHDL language, communica...

In this paper we present an approach to accelerate the simulation speed of behavioral VHDL system descriptions through the use of hardware support1. The method allows source level debugging of behavioral, algorithmic VHDL in a way similar to source level debugging known from software programming languages. We can set breakpoints in the source code and evaluate the contents of variables by readi...

A number of proposals for object-oriented extensions to VHDL deal with object-oriented extensions to support high-level modeling of data. They provide features for expressing data abstraction, encapsulation, and inheritance with polymorphism— features that are central to object oriented techniques. There are two approaches to object-oriented data modeling: class-based and programming by extensi...