This paper proposes the integration of two systems engineering analysis tools, the Design Structure Matrix (DSM) and Network Analysis (NA), to study task interactions in a Product Development Process (PDP). The DSM is a matrix-based systems engineering tool that analyzes task sequences to improve PDP execution. Using NA metrics to measure properties of information flow helps to identify importa...

We present a radix-4 static CMOS full adder circuit that reduces the propagation delay, PDP, and EDP in carry-based adders compared with using a standard radix-2 full adder solution. The improvements are obtained by employing carry look-ahead technique at the transistor level. Spice simulations using 45 nm CMOS technology parameters with a power supply voltage of 1.1 V indicate that the radix-4...

The power-delay product is a direct measurement of the energy expanded per operational cycle of an arithmetic circuit. Lowering the supply voltage of the full adder cell to achieve low power-delay product is a sensible approach to improve the power efficiency at sustainable speed of arithmetic circuits composed of such instances at high level design. In this paper, a novel design of a low power...

Industrial wireless channel modeling is essential for the development of industrial internet things (IIoT) systems. Moreover, millimeter-wave (mmWave) bands have a high potential to be used IIoT applications because their data-rates and better applicability having multiple antennas. As result, we introduce an exemplar extraction approach applied on mmWave measurements. A machine learning (ML) c...

A novel synchronous dual-bit adder design, realized using the elements of commercial standard cell libraries is presented in this article. The adder embeds two-bit carry look-ahead generator functionality and is realized using simple and compound gates of the standard cell library. The performance of the proposed dualbit adder design is evaluated and compared vis-à-vis the conventional full add...

Combination of 3D IC technology and network on chip (NoC) is an effective solution to increase system scalability and also alleviate the interconnect problem in large scale integrated circuits. However, due to the increased power density in 3D NoC systems and the destructive impact of high temperatures on chip reliability, applying thermal management solutions becomes crucial in such circuits. ...

This paper extends the power hierarchy of dependability models developed by Malhotra and Trivedi (1994) and Muppala et al. (2000) to include Piecewise Deterministic Markov Processes (PDP) and PDP-related Petri Nets. PDPs are known as the largest class of continuous-time hybrid state Markov processes not involving diffusions. Since Petri Nets have proven to be extremely useful in developing Mark...

A Fault tolerant reversible logic has gained importance as they consume low power and less heat dissipation. The benefits of logical reversibility can be gained only after employing physical reversibility. Every future technology will have to use reversible gates in order to reduce power. This paper proposed a new fault tolerant reversible 4*4 RR-gate which satisfies the reversible and parity p...

http: // www.ijrsm.com © International Journal of Research Science & Management [48] PERFORMANCE ANALYSIS OF HIGH SPEED CMOS FULL ADDER CIRCUIT FOR LOW VOLTAGE VLSI CIRCUIT DESIGN IN NANOMETER Anuj Dev & Sandip Nimade Technocrats Institute of Technology Bhopal, India DOI: 10.5281/zenodo.569383 Abstract As the technology scaling reduces the gate oxide thickness and the gate length thereby increa...

After decades of research and development, plasma displays are finally beginning to appear in the commercial and consumer markets. Following a short review on the basic principles of direct and alternating current plasma displays, we present a summary of the status of color plasma displays. Plasma display panels (PDPs) have finally achieved luminance and efficiency values on par with hi-definit...