Delay testing of combinational logic in a clocked environment is analyzed. A model based upon paths is introduced for delay faults. Any path with a total delay exceeding the clock interval is called a "path fault." This is a global delay fault model because it is associated with an entire path. The more familiar slow-to-rise or slow-to-fall gate delay fault, on the other hand, is a local fault ...

Excessive voltage drops in power and ground (P&G) buses of CMOS VLSI circuits can severely degrade both design reliability and performance. Maximum current estimates are needed in the circuit to accurately determine the impact of these problems. In [1], a pattern-independent, linear time algorithm (iMax) is described that is very e ective in estimating the maximum current waveforms at various c...

Non zero signal rise and fall times contribute significantly to CMOS gate performances such as propagation delay or short circuit power dissipation. We present a closed form expression to model output rise and fall times in deep submicron CMOS structures. The model is first developed for inverters considering fast and slow input ramp conditions. It is then extended to gates through a reduction ...

In digital CMOS circuits, parametric yield improvement may be achieved by reducing the variability of performance and power consumption of individual cell instances. Such improvement of variation robustness can be attained by evaluating parameter variation impact at gate level. Statistical characterization of logic gates are usually obtained by computationally expensive electrical simulations. ...

We propose a new timing error detector for timing tracking loops inside the Rake receiver in spread spectrum systems. Based on a particle filter, this timing error detector jointly tracks the delays of each path of the frequency-selective channels. Instead of using a conventional channel estimator, we have introduced a joint time delay and channel estimator with almost no additional computation...

|In this paper we present a Low Voltage Diierential Current Switch Logic (LVDCSL) gate which is capable of achieving high performance for large fan-in gates. High fan-in is enabled by allowing large stacked NMOS tree heights using a pre-discharged NMOS tree, at the same time the power penalty of an increased number of internal nodes in the gate is mitigated by restricting internal node voltage ...

Non zero signal rise and fall times contribute significantly to CMOS gate performances such as propagation delay or short circuit power dissipation. We present a closed form expression to model output rise and fall times in deep submicron CMOS structures. The model is first developed for inverters considering fast and slow input ramp conditions. It is then extended to gates through a reduction ...

We present a detailed error analysis of a Rydberg blockade mediated controlled-NOT quantum gate between two neutral atoms as demonstrated recently in Isenhower et al. [Phys. Rev. Lett. 104, 010503 (2010)] and Zhang et al. [ Phys. Rev. A 82, 030306 (2010)]. Numerical solutions of a master equation for the gate dynamics, including all known sources of technical error, are shown to be in good agre...

We present a timed automaton-based method for accurate computation of the delays of combinational circuits. In our method, circuits are represented as networks of timed automata, one per circuit element. The state space of the network represents the evolution of the circuit over time and delay is computed by performing a symbolic traver-sal of this state space. Based on the topological structur...