this paper presents a novel control method to improve the efficiency of low-voltage dc-dc converters at light loads. pulse width modulation (pwm) converters have poor efficiencies at light loads, while pulse frequency modulation (pfm) control is more efficient for the same cases. switching losses constitute a major portion of the total power loss at light loads. to decrease the switching losses...

A novel ultra-high compliance, low power, very accurate and high output impedance current output stage (COS) with extremely high output current drive capability is proposed in this paper. The principle of operation of this unique structure is discussed, its most important formulas are derived and its outstanding performance is verified by HSPICE simulation in TSMC 0.18µm CMOS, BSIM3, and Level4...

A 256 144-bit TCAM is designed in 0.18m CMOS. The proposed TCAM cell uses 4T static storage for increased density. The proposed match-line (ML) sense scheme reduces power consumption by minimizing switching activity of search-lines and limiting voltage swing of MLs. The scheme achieves a match-time of 3 ns and operates at a minimum supply voltage of 1.2 V.

Since the early 1900s, single series diode rectifiers have long been used in amplitude modulation signal detection. One may think that their design theory is already well matured. Let us check and see if true.

This paper proposes a stand-alone photovoltaic (PV) system based on a DC-DC positive output super lift Luo (POSLL) converter. A conventional sliding mode control, a sliding mode controller using a simple sign function and a linear controller using proportional integrator (PI) are used for the control of the PV panel voltage and POSLL converter inductor current and these methods are compared tog...

This paper presents different types of bipolar Pulse Width Modulation (PWM) strategies for the chosen Cascaded MultiLevel Inverter (CMLI). The main purpose of MLI is to use power semiconductor devices of lower voltage ratings to realize high voltage levels at inverter output. Due to their ability to obtain refined output voltage waveforms, reduced Total Harmonic Distortion (THD) and reduced EMI...

This paper presents a fully integrated linear Hall sensor by means of 0.8 μm high voltage complementary metal-oxide semiconductor (CMOS) technology. This monolithic Hall sensor chip features a highly sensitive horizontal switched Hall plate and an efficient signal conditioner using dynamic offset cancellation technique. An improved cross-like Hall plate achieves high magnetic sensitivity and lo...

On-chip networks have emerged as a scalable and high-bandwidth communication fabric in many-core processor chips. However, the energy consumption of these networks is becoming comparable to that of computation cores, making further scaling of core counts difficult. This thesis makes several contributions to low-swing signaling circuit design for the energy efficient on-chip networks in two sepa...

In this paper, a new cascaded multilevel inverter by capability of increasing the number of output voltage levels with reduced number of power switches is proposed. The proposed topology consists of series connection of a number of proposed basic multilevel units. In order to generate all voltage levels at the output, five different algorithms are proposed to determine the magnitude of DC volta...