Stochastic estimates of wire-length based on Rent’s rule predict a benefit of 3D integration over traditional ICs, tapering off with a 50% reduction for 8 tiers. However, Rent’s rule is unnecessarily pessimistic, because it assumes an extrapolation of architectures that were conceived in two dimensions. This paper examines the gains possible in several 3D interconnect network topologies. Placem...

As VLSI technology enters the nanometer era, the supply voltage is continually dropped. This condition helps to reduce the power dissipation, but make the power integrity problem become worse. Employing decoupling capacitances (decap) at floorplan stage has been a common approach to alleviate the supply noise problem. However, the decap budget is often overly estimated in previous researches. B...

Modern Integrated Circuits’ reliability and performance mainly depends upon its temperature and power due to the continuous process scaling. The IC peak temperature depends upon the power density of the IC. Thus, a power-aware High-Level Synthesis technique concentrates on the overall power reduction and is not appropriate for temperature-aware IC design. The temperature-aware design technique ...

Dedicated to my family, who have always put up with me. iii ACKNOWLEDGEMENTS I would like to express my sincere gratitude to Professor Sung Kyu Lim for his guidance of my research and his patience during my studies at Georgia Tech. I would like to thank my thesis committee members, their valuable suggestions. I would like to thank all the members of GTCAD and CREST groups for their support and ...

Existing scrubbing techniques for SEU mitigation on FPGAs do not guarantee an error-free operation after SEU recovering if the affected configuration bits do belong to feedback loops of the implemented circuits. In this paper, we a) provide a netlist-based circuit analysis technique to distinguish so-called critical configuration bits from essential bits in order to identify configuration bits ...

In this paper, we present a complete chip design method which incorporates a soft-macro placement and resynthesis method in interaction with chip floorplanning for area and timing improvements. We present a performance-driven soft-macro clustering and placement method which preserves hardware descriptive language (HDL) design hierarchy to guide the soft-macro placement process. We develop a tim...

Vertical integration (3D ICs) has demonstrated the potential to reduce inter-block wire latency through flexible block placement and routing. However, there is an untapped potential for 3D ICs to reduce intra-block wire latency through architectural designs that can leverage multiple silicon layers in innovative ways. Furthermore, it is particularly challenging to simultaneously explore the phy...

Design for yield (DFY) problems have received increasing attention. Of particular concern in DFY problems is how to formulate and reduce a critical area for random defects. Arranging interconnects is recognized as an effective means of improving the sensitivity towards random defects. Previous works have demonstrated that random defects significantly influence interconnections and the effective...

In floorplanning, it is common that a designer wants to have certain modules abutting with one another in the final packing. The problem of controlling the relative positions of an arbitrary number of modules in floorplan design is nontrivial. Slicing floorplan has an advantageous feature in which the topological structure of the packing can be found without knowing the module dimensions. This ...