This paper presents an all-digital multiphase delay-locked loop (ADMDLL) for wide-locking range and micro-power applications. To enhance locking range and locking speed of the ADMDLL, we proposed the adaptive successive approximation register-controlled (ASAR) algorithm, which uses the frequency-estimation selector (FES) to avoid harmonic lock issue. In addition, the FES can reuse the delay lin...

This paper describes the implementation of a SPI-programmable clock delay chip based on a Delay Locked Loop (DLL) in order to shift the phase of the LHC clock (25 ns) in steps of 1ns, with less than 5 ps jitter and 23 ps of DNL. The delay lines will be integrated into ICECAL, the LHCb calorimeter front-end analog signal processing ASIC in the near future. The stringent noise requirements on the...

This paper presents a low-complexity real-time single-tone phase and frequency estimation technique based on zero-crossing detection and linear regression. The proposed zerocrossing phase and frequency estimator fills a gap between lowcomplexity phase locked loop estimation and high-performance maximum likelihood estimation. Similar to a phase locked loop, the zero-crossing phase and frequency ...

Frequency synthesis is one of the most important and most actively researched subjects in the field of VLSI mixed-signal circuit design. Among the existing techniques in this area, phase locked loop fractional architecture is a widely used one for generating frequencies which are not integer multiple of the input reference frequency. Flying-Adder architecture is an emerging technique which is b...

Fine-grain Dynamic Voltage and Frequency Scaling (DVFS) is becoming a requirement for Globally-Asynchronous Locally-Synchronous (GALS) architectures. However, the area overhead of adding voltage and frequency control engines in each voltage and frequency island must be taken into account to optimize the circuit. A small-area fast-reprogrammable Digital Frequency-Locked Loop (DFLL) engine is a s...

During neoplastic transformation, cells can promote their own growth by activating proto-oncogenes. Reporting in Cell, Iliopoulos et al. (2009) now show that in certain cell types, a transient oncogenic signal is sufficient to induce neoplastic transformation and to maintain it through a positive feedback loop driven by the inflammatory cytokine interleukin-6.

In this paper a new variety of the digitized version of an analog phase locked loop has been proposed in order to overcome the conditionally stable nature of a software controlled phase locked loop. Also the conventional need of a low pass filter to filter out the high frequency components at the output of a phase detector is avoided through the use of In-phase and Quadrature signals. MATLAB si...

The CD4046BC micropower phase-locked loop (PLL) consists of a low power, linear, voltage-controlled oscillator (VCO), a source follower, a zener diode, and two phase comparators. The two phase comparators have a common signal input and a common comparator input. The signal input can be directly coupled for a large voltage signal, or capacitively coupled to the self-biasing amplifier at the sign...