We describe a system for simulating and generating accurate tests for bridging faults in CMOS ICs. After introducing the Primitive Bridge Function, a characteristic function describing the behavior of a bridging fault, we present the Test Guarantee Theorem, which allows for accurate test generation for feedback bridging faults via topological analysis of the feedback-innuenced region of the fau...

We review the main difficulties and advantages in developing CMOS ternary circuits. In addition to employing multiple power sources and multiple thresholds, we describe a new theory of transmission functions for designing CMOS ternary logic circuits. It can explain the main CMOS ternary circuits proposed previously. Computer simulations show that the circuits based on the transmission-function ...

In recent years, there have been major advances in CMOS VLSI technology, which generated great interest in electronic circuits, which is more efficient by perfection performance and power consumption. Circuits, called multi valued logic circuits offer several potential opportunities for improvement of present vlsi designs. Current mode CMOS multivalued logic circuits are interesting and have ma...

This paper discusses architectural and circuit-level aspects related to hardware realizations of fuzzy controllers. A brief overview on fuzzy inference methods is given focusing on chip implementation. The singleton or zero-order Sugeno’s method is chosen since it offers a good trade-off between hardware simplicity and control efficiency. The CMOS microcontroller described herein processes info...

Field-effect transistors based on carbon nanotubes have been shown to be faster and less energy consuming than their silicon counterparts. However, ensuring these advantages are maintained for integrated circuits is a challenge. Here we demonstrate that a significant reduction in the use of field-effect transistors can be achieved by constructing carbon nanotube-based integrated circuits based ...

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Very Low Voltage (VLV) testing has been proposed to increase flaw detection in bulk silicon CMOS integrated circuits and this paper explores these and additional advantages in the context of testing Silicon-On-Insulator (SOI) integrated circuits. In the VLV regime, the history effect, which describes how delays through SOI circuits vary based on a circuit’s recent switching history, is amplifie...

Today, an electron spin qubit on silicon appears to be a very promising physical platform for the fabrication of future quantum microprocessors. Thousands these qubits should packed together into one single die in order break supremacy barrier. Microelectronics engineers are currently leveraging current CMOS technology design manipulation and read-out electronics as cryogenic integrated circuit...

The asynchronous circuit design paradigm provides a practical solution for several challenges and constraints of current and future technologies to build integrated circuits and systems. However, there is little electronic design automation support for this paradigm. This work presents a standard cell library designed to support a semi-custom approach in the design of asynchronous integrated ci...

An approach is presented for the analysis of the nonlinear behavior of analog integrated circuits. The approach is based on a variant of the Volterra series approach for frequencydomain analysis of weakly nonlinear circuits with one input port, such as amplifiers, and with more than one input port, such as analog mixers and multipliers. By coupling numerical results with symbolic results, both ...