As single electron tunneling technology based threshold logic gate uses less no of tunnel junctions so it reduces the size of Boolean logic gate compare to single electron tunneling based logic gate and single electron transistor based logic gate. The design and simulation of a 4:1 multiplexer based on buffered threshold logic gate is presented in this paper. The logic operation is verified usi...

Most recent works on soft errors only address circuit reliability under single gate errors caused by SEUs. In this paper, we compare the probabilities of single and multiple errors. We formulate a criterion based on gate error probabilities for considering multiple gate errors in circuit reliability. Gate error probabilities are increased by technology trends such as the down-scaling of device ...

This paper describes a Spicexompatible circuit reliability simulation model of submicron LDD MOS devices. It incorporates an accurate hot carrier model of the degraded MOSFEX characteristics under long term operations, which includes a drain current model and a substrate current model. The drain current reduction is modeled as mobility degradation due to interface states enhanced scattering. Th...

Balanced gates are an effective countermeasure against power analysis attacks only if they can be guaranteed to maintain their power balance. Traditional testing and reliability methods are used primarily only to ensure the correctness of the logical functionality and not the balance of a circuit. Due to the hardware redundancy in balanced gate designs, there are many faults which can imbalance...

The stability, reliability and miniaturization of fiber optic gyroscope (FOG) are always the research focuses and difficulties. This paper presented a hardware design method for the digital closed loop control system of FOG based on FPGA. Based on a large number of experiments, this paper summarized the parameter demands for each module of closed loop control circuit and designed a correspondin...

Negative bias temperature instability (NBTI) has become a critical reliability phenomena in advanced CMOS technology. In this paper, we propose an analytical temperature-aware dynamic NBTI model, which can be used in two circuit operation cases: executing tasks with different temperatures, and switching between active and standby mode. A PMOS Vth degradation model and a digital circuits’ tempor...

On-chip circuit aging sources, like negative bias temperature instability (NBTI), hot-carrier injection (HCI), electromigration, and oxide breakdown, are reducing expected chip lifetimes. Being able to track the actual aging process is one way to avoid unnecessarily large design margins. This work proposes a sensing scheme that uses sets of reliability sensors capable of accurately tracking NBT...

Higher levels of integration have led to a generation of integrated circuits for which power dissipation and reliability are major design concerns. In CMOS circuits, both of these problems are directly related to the extent of circuit switching activity. The average number of transitions per second at a circuit node is a measure of switching activity thit has been called the transition density....

Traditionally, research into circuit-switched (C-S) communication networks has been divided into two areas, reliability and performance, each making little reference to the other. More recently, however, research has focused on unification of the two. One possible choice for a combined performance and reliability measure is the network grade-of-service (NGOS), i.e. the overall probability of bl...

In this paper, we describe a comprehensive layout methodology for bonded three-dimensional integrated circuits (3D ICs). In bonded 3D integration technology, parts of a circuit are fabricated on different wafers, and then, the wafers are bonded with a glue layer of Cu or polymer based adhesive. Using our layout methodology, designers can layout such 3D circuits with necessary information on int...