The integrity and issues related performance associated with scaling Si MOSFET channel length promotes research in new device SOI, double gate and GAA MOSFET. In this paper, we pr novel characteristic of horizontal rectangular gate MOSFETs with dual metal of gate we obtained using SILVACO TCAD tools. We will also exhibit some simulation results we obtained relating to the influence of some para...

This paper presents device simulations on the vertical silicon nanowire tunneling FET (VSiNW TFET). Simulations show that a narrow nanowire and thin gate oxide is required for good performance, which is expected even for conventional MOSFETs. The gate length also needs to be more than the nanowire diameter to prevent short channel effects. An effect more unique to TFET is the need for abrupt so...

We demonstrated a nanowire gate-all-around (GAA) negative capacitance (NC) tunnel field-effect transistor (TFET) based on the GaAs/InN heterostructure using TCAD simulation. In gate stacking, we proposed tri-layer HfO2/TiO2/HfO2 as high-K dielectric and hafnium zirconium oxide (HZO) ferroelectric (FE) layer. The GAA-TFET overcomes thermionic limitation (60 mV/de...

In this work, the frequency response of gate-all-around (GAA) Ge/GaAs heterojunction tunneling field-effect transistor (TFET) with hetero-gate-dielectric (HGD) and pnpn channel doping profile has been analysed by technology computer-aided design (TCAD) device-circuit mixed-mode simulations, with comparison studies among ppn, pnpn, and HGD pnpn TFET devices. By recursive tracing of voltage trans...

Nanowire (NW) devices, particularly the gate-allaround (GAA) CMOS architecture, have emerged as the frontrunner for pushing CMOS scaling beyond the roadmap. These devices offer unique advantages over their planar counterparts which make them feasible as an option for 22-nm and beyond technology nodes. This paper reviews the current technology status for realizing the GAA NW device structures an...

We present a facile CMOS-compatible fabrication of lateral gate-all-around (GAA) field effect transistors (FETs) based on concentric Si-SiO₂/N(++)Si core-multi-shell nanowires (NWs). Si-SiO₂/N(++)Si core-multi-shell NWs were prepared by sequential Si NW growth, thermal oxidation and Si deposition processes in a single chamber. The GAA NW FET was then fabricated using the Si core, SiO₂ inner-she...

0038-1101/$ see front matter 2010 Elsevier Ltd. A doi:10.1016/j.sse.2010.04.037 * Corresponding author. Tel.: +41 21 693 5633; fax E-mail address: [email protected] (M This paper reports all-silicon asymmetrically strained Tunnel FET architectures that feature improved subthreshold swing and Ion/Ioff characteristics. We demonstrate that a lateral strain profile corresponding to at leas...

This paper examines the performance of a Gate-Engineered Gate-All-Around Charge Plasma Nanowire Field Effect Transistor (GAA-DMG-GS-CP NW-FET) and implementation common source (CS) amplifier circuit. The proposed GAA-DMG-GS-CP NW-FET incorporates dual-material gate (DMG) stack (GS) as engineering techniques its analog/RF parameters are compared to those Single-Material Gate (GAA-SMG-CP device. ...

III–V semiconductors, especially InAs, have much higher electron mobilities than Si and have been considered as promising candidates for n-channel materials for post-Si lowpower CMOS logic applications. Combined with the inherent 3-D structure that enables the gate-all-around (GAA) geometry for superb gate electrostatic control, III–V nanowire (NW) MOSFETs are well positioned to extend the scal...

The inter-band tunnel transistor (TFET) architecture features a subkT/q sub-threshold slope operation and can potentially support high ION/IOFF ratios over small gate voltages. Based on twodimensional numerical simulations, we investigate TFET in various material systems ranging from silicon to indium arsenide. TFET performance can be enhanced when heterojunctions are employed at the source sid...