The complexity and routability of layout depends on the number of layers, which can be used for the completion of interconnections. The global routing can be solved by graph based techniques. Efficient 3D routing methods are efficient to minimize the via overflows and total number of vias. The minimization methods rip-up and reassignment for a integer programming based layer assignment. Benchma...

In the next generation Internet protocol (IPv6), mobility is supported by means of Mobile IPv6 (MIPv6). As a default part of the MIPv6 protocol, route optimization is used to route packets directly to a mobile node’s currently used address at the mobile node’s visited subnet. Return Routability is the protocol suggested by the IETF for managing this task. Route optimization is often carried out...

The global routing problem decomposes the large, complex routing problem into a set of more manageable subproblems. The high correlation between the output of the global router and the detailed router enables the designer to efficiently use the global route to refine the design quickly before running the full detailed route. Hence, routability of the global routing solution is the key factor. T...

This paper explores the relationship between the routability of a field-programmable gate array (FPGA) and the flexibility of its interconnection structures. The flexibility of an FF’GA is determined by the number and distribution of switches used in the interconnection. While good routability can be obtained with a high flexibility, a large number of switches will result in poor performance an...

Reconfigurable systems employ highly-routable local routing architecture to interconnect generic fine-grain logic blocks. Commercial FPGAs employ 50% sparse crossbars rather than fully-connected crossbars in their local routing architecture to trade off between the area and routability of the Logic Blocks (LBs). While the input crossbar provides good routability and logic equivalence for the in...

In segmented channel routing of row-based FPGAs, the routability and interconnection delays depend on the choice of the upper bounds on the number of programmable switches used in routing net segments in the channel. Traditionally, the upper bounds for the net segments in the same channel are set uniformly. In this paper, we present algorithms for determining the upper bounds for all net segmen...

Routability, signal integrity and manufacturability are important issues in physical design and congestion reduction is a widely used method for ameliorating these problems in current design methodologies. Besides, routing congestion may create large delays in detoured global wires that can be avoided by congestion reduction. In recent years, asynchronous serial transceivers are proposed for da...

modern integrated circuits consist of millions of standard cells and routing paths. in nano-scale designs, mis-prediction is a dominant problem that may diminish the quality of physical design algorithms or even result in the disruption of the convergence of the design cycle. in this paper, a new planning methodology is presented in which a master-plan of the chip is constructed at the early le...