Flash ADC is an important component for realization of high speed and low power devices in signal processing system .As technology scale down, leakage current becomes the most concerned factor. This paper reports the power gating technique to provide the reduction mechanism for suppressing the leakage current effectively during standby mode but it introduces ground bounce noise. We designed a “...

Deep Sub-Micron SRAM Design for Ultra-Low Leakage Standby Operation by Huifang Qin Doctor of Philosophy in Engineering Electrical Engineering and Computer Sciences University of California, Berkeley Professor Jan M. Rabaey, Chair Suppressing the standby current in memories is critical in low-power design. By lowering the supply voltage (VDD) to its standby limit, the data retention voltage (DRV...

Design complexity is increasing day by day in modern digital systems. Due to reconfigurable architecture, low non recurring engineering (NRE) and ease of design field programmable gate arrays (FPGA) become a better solution for managing increasing design complexity. Due to scaling trends FPGA uses more transistors which increase the leakage current. FPGAs are well suited for wireless applicatio...

Multi-threshold voltage CMOS (MTCMOS) is an effective technique for suppressing the leakage currents in idle circuits. When the conventional MTCMOS technique is directly applied to a sequential circuit however the stored data is lost during the low-leakage sleep mode. Significant energy and timing penalties are suffered to restore the pre-sleep system state at the end of the sleep mode with the...

An analytical model for 1/f gate noise is developed and applied to the simulation and the characterization of ultra-thin MOSFETs. The proposed model is based on oxide trapping mechanisms and uses the concept of equivalent flat band voltage fluctuations. The developed model reproduces experimental behaviors. The power spectral density of flat band voltage fluctuation extracted from gate current ...

In this paper we propose a new model for leakage mechanism in tail-mode bits of DRAM data retention characteristics. For main-mode bits, leakage current can be attributed to junction thermal-generation leakage current. For tail-mode bits, it is found for the first time that Gate-Induced Drain Leakage (GIDL) current has a dominant impact. The root cause is electric field enhancement caused by me...

Gallium arsenide junction field-effect transistors (GaAs JFETs) can be made immune to carrier freeze-out, making such transistors useful for the readout of detector arrays that operate at 4 K. Typical applications require transistors with very low noise and extremely low leakage current. By using a recently developed etchant for GaAs that is highly isotropic, etched GaAs JFETs have fabricated t...

On-chip power consumption is one of the fundamental challenges of current technology scaling. Cache memories consume a sizable part of this power, particularly due to leakage energy. STT-RAM is one of several new memory technologies that have been proposed in order to improve power while preserving performance. It features high density and low leakage, but at the expense of write energy and per...

Mobile computing and mobile communication applications which are powered by battery, the battery life is a major concern. Leakage power dissipation is critical in VLSI circuits as the battery leaks even when devices are in idle state. To reduce leakage power as well as total power in CMOS logic gates and circuits a new circuit technique called LPSR Technique is proposed in this paper. Earlier w...