This study introduces a reversible optical fulladder. Also optical NOT and NOR gates are implemented through Electro-Absorption-Modulator / Photo Detector (EAM/PD) pairs, were utilized for fulfilling reversible R gate. Then, reversible fulladder was designed based on the proposed reversible optical R gate. The operation of the suggested fulladder was simulated using Optispice and it was fou...

In this work, the design and analysis of new Level Shifter with Gate Driver for Li-Ion battery charger is proposed for high speed and low area in 180nm CMOS technology. The new proposed level shifter is used to raise the voltage level and significantly reduces transfer delay 1.3ns (transfer delay of conventional level shifter) to 0.15ns with the same input signal. Also, the level shifter with g...

As semiconductor manufacturing entered into nanoscale era, performance degradation due to Negative Bias Temperature Instability (NBTI) became one of the major threats to circuits reliability. In this paper, we present a model and analysis of NBTI impact on circuit delays. First, we model NBTI impact on gate intrinsic delay and output transition delay. The insights of our models reveal that NBTI...

In this report, a parameter extraction procedure and a model presented in [4] are tested using a 280×0.25μm transistor manufactured in a 0.25 μmCMOS process. The extraction procedure is based on two sets of S-parameter measurements. The first transistor measurement is in the linear region, to obtain the extrinsic terminal resistances which are biasindependent . The intrinsic parameters of the t...

In this paper a new architecture for delay locked loops will be presented.  One of problems in phase-frequency detectors (PFD) is static phase offset or reset path delay. The proposed structure decreases the jitter resulted from PFD by switching two PFDs. In this new architecture, a conventional PFD is used before locking of DLL to decrease the amount of phase difference between input and outpu...

The e!ect of interconnect coupling capacitance on the transient characteristics of a CMOS logic gate strongly depends upon the signal activity. A transient analysis of CMOS logic gates driving two and three coupled resistive}capacitive interconnect lines is presented in this paper for di!erent signal combinations. Analytical expressions characterizing the output voltage and the propagation dela...

The performance of carbon nanotube field-effect transistors is analyzed, using the nonequilibrium Green’s function formalism. The role of the inelastic electron-phonon interaction on the both on-current and gate delay time of these devices is studied. For the calculation of the gate delay time the quasi-static approximation is assumed. The results confirm experimental data of carbon nanotube tr...

A model for the delay of neuron-MOS (neuMOS) and Capacitive Threshold-Logic (CTL) based logic circuits is presented for the first time. It is based on the analysis of the basic neuron-MOS [l] and CTL gate structures [a]. A closed form analytic expression for the delay of the threshold gate is derived. A relation for the delay in terms of an ordinary CMOS inverter delay expressed as a function o...

This work investigates the channel thickness dependency of high-k gate dielectric-based complementary metal-oxide-semiconductor (CMOS) inverter circuit built using a conventional double-gate metal gate oxide semiconductor field-effect transistor (DG-MOSFET). It is espied that the use of high-k dielectric as a gate oxide in n/p DG-MOSFET based CMOS inverter results in a high noise margin as well...