A single-stage 24 GHz triple stacked power amplifier using 0.13 μm CMOS process is demonstrated. To Compare with parallel current combining method, series voltage combining method using a stacked amplifier architecture can realize a large output voltage swing from the top transistor without exceeding the transistor breakdown voltage limitations. However, at high frequencies, parasitic capacitan...

This article proposed a simple self cascode RGC amplifier configuration to increase the gain and bandwidth. The cascode amplifier eliminates the miller capacitance between input and output and facilitates high gain, high input and output impedance with high bandwidth. However, the cascode amplifier requires relatively high supply voltage for proper operation and it decreases the output voltage ...

A novel low-voltage two-stage operational amplifier employing resistive biasing is presented. This amplifier implements neutralization and correction common mode stability in second stage while employs capacitive dc level shifter and coupling between two stages. The structure reduces the power consumption and increases output voltage swing. The compensation is performed by simple miller method....

A novel low-voltage two-stage operational amplifier employing resistive biasing is presented. This amplifier implements neutralization and correction common mode stability in second stage while employs capacitive dc level shifter and coupling between two stages. The structure reduces the power consumption and increases output voltage swing. The compensation is performed by simple miller method....

A low-voltage compatible 120dB gain two-stage amplifier in standard digital CMOS with 3 transistors between VDD and VSS is presented and circuit details are discussed. With the use of precision voltage attenuator, output level monitoring circuits (OLMC) and a digital tuning network, the first stage was tested, achieving ≥76dB DC gains over 2Vpp output swing. With a modest-gain 2nd stage, ≥120dB...

An accurate, wide output swing, low voltage charge pump is proposed. It is based on a second generation current conveyor which is used to equate charging and discharging currents. A low voltage enhanced current mirror ensures matching between nominal and output currents and current steering is used to minimize charge sharing. Simulation results characterize performance of the proposed circuit.

Floating Gate MOS (FGMOS) transistors can be very well implemented in lieu of conventional MOSFET for design of a low-voltage, low-power current mirror. Incredible features of flexibility, controllability and tunability of FGMOS yields better results with respect to power, supply voltage and output swing. This paper presents a new current mirror designed with FGMOS which exhibit high output imp...

With a 3.3-V interface, such as PCI-X application, high-voltage overstress on the gate oxide is a serious reliability problem in designing I/O circuits by using only 1/2.5-V low-voltage devices in a 0.13m CMOS process. Thus, a new output buffer realized with low-voltage (1and 2.5-V) devices to drive high-voltage signals for 3.3-V applications is proposed in this paper. The proposed output buffe...

This paper focuses a hetero gate material dielectric DG TFET with low band gap source material, which offers high / on off I I ratio, sub 60mV/dec subthreshold swing along with significant improvement in on current. Here analytical model for 2D electric field is derived from Poisson’s equation and is used to determine the subthreshold swing, transconductance, output conductance, gate threshold ...

The aim of this paper is to model and characterize the current voltage characteristics of Schottky Barrier (SB) Carbon NanoTube Field Effect Transistors (SB-CNTFETs) below and above threshold, in order to evaluate the noise margin and output voltage swing, whose values are necessary in the design of digital circuits.