This letter presents an inductor-loaded 2:1 regenerative frequency divider operating up to 331.2 GHz in an InP HBT process, which, to the best of authors’ knowledge, is the fastest frequency divider reported thus far. On-wafer measurement shows that the divider is operating from 304.8 GHz to 331.2 GHz, with output power from 27 dBm to 12.3 dBm (no probe loss correction), while dissipating 85.5 ...

This work proposes an integrated high frequency divider with an inductive peaking technique implemented in a current mode logic (CML) frequency divider. The proposed divider is composed with a master-slave flip-flop, and the master-slave flip-flop acts as a latch and read circuits which have the differential pair and cross-coupled n-MOSFETs. The cascode bias is applied in an inductive peaking c...

In this paper design and simulation of a 4.3 – 5.4 GHz LC digitally controlled oscillator (LC DCO) in IBM 7RF 0.18μm CMOS technology are presented. Wide gigahertz tuning range is achieved by using two LC DCOs, sharing same structure. DCO is made of one NMOS negative impedance transistor pair and LC tank, which consists of high quality inductor and two switched capacitor arrays for coarse and fi...

A frequency divider based on injection-locked tunable ring oscillator is designed on 0.13-μm standard CMOS. The proposed design can achieve divide-by-4 in the frequency range of 58.75-66.3 GHz. The divider dissipates 49.5 to 54.5 mW power from a 1.5-V voltage supply. Key-Words: High-speed frequency dividers, Injection-locked tunable ring oscillator, Division range

The implementation of a programmable high speed divider for a CMOS Frequency Synthesizer, using 0.35 μm CMOS technology, is described. The Frequency Synthesizer is part of a RF transceiver to work in the 2.4 GHz ISM (Industrial, Scientific and Medicine) band. The programmable divider employs: a divide-by-32/33 dual-modulus prescaler composed by a divide-by-4/5 synchronous counter, using the Ext...

This paper proposes an idea to modify the conventional Wilkinson power dividers to have physically spaced output ports. The well-known internal resistor of Wilkinson power divider is now connected to output ports by two additional transmission lines to create a triangular shape power divider. Several modified power dividers are designed at frequency of 1.0 GHz and one of them is fabricated and ...

An 8-bit programmable square finder cum frequency divider architecture is presented. This special architecture includes a high speed parallel counter, clock trigger circuit, eight bit multiplier logic, sequence termination logic and sequence restarter logic. The entire architecture is divided into two parts: The frequency divider section and the square finder section. The frequency divider circ...

The letter describes a novel, continuum-based approach, to capture the evolution of electromechanical dynamics in power network following disturbance. Such approach is based on frequency divider formula (FDF) , which was recently proposed by third author. A key point obtaining frequency (FDF) a...

-A lumped element 180 Wilkinson divider consisting of 11 elements was presented in 2003. It used a conventional Wilkinson divider, a -90 and a +90 phase shifter of πand T-type. In this paper, that of 10 elements is newly presented. Frequency characteristics of the two 180 Wilkinson dividers and those of a rat-race divider known as an out of phase circuit are discussed. Key-Words: Wilkinson divi...

We present a scalable high-speed divide-by-N frequency divider using only basic digital CMOS circuits. The divider achieves high-speed operation using a novel parallel counter and a pipelined architecture. The parallel counter is based on a state look-ahead component in conjunction with an internal pipeline structure in order to simultaneously trigger all state value updates without a rippling ...