To truly exploit FPGAs for rapid turn-around development and prototyping, placement times must be reduced to seconds; latebound, reconfigurable computing applications may demand placement times as short as microseconds. In this paper, we show how a systolic structure can accelerate placement by assigning one processing element to each possible location for an FPGA LUT from a design netlist. We ...

Increasing the performance of uniprocessor systems is becoming increasingly difficult. As a result, processor systems are moving towards chip multiprocessor designs. Because of this trend, parallel programming design is becoming increasingly important. This presents new issues for complex software optimized for uniprocessor performance. CAD tools for placing and routing of FPGA designs are an e...

Area utilization is poor in reconfigurable operating systems due to fragmentation of placement resources caused by dynamic addition and deletion of tasks. We attempt to quantify the amount of fragmentation of the area resources. Main assertion of our fragmentation model is that each empty cell on the FPGA offers different fragmentation depending upon other empty cells in its vicinity. Our model...

Field-programmable gate arrays (FPGAs) have the potential to address scaling challenges in CMOS technology because of their regular structures and the flexibility they possess by being re-configurable after fabrication. One of the potential approaches in attacking scaling challenges, such as negative-bias temperature instability (NBTI) and process variation (PV), is by using placement technique...

With the arrival of partial reconfiguration technology, modern FPGAs support tasks that can be loaded in (removed from) the FPGA individually without interrupting other tasks already running on the same FPGA. Many online task placement algorithms designed for such partially reconfigurable systems have been proposed to provide efficient and fast task placement. In these algorithms, the resource ...

Field-Programmable Gate Arrays (FPGAs) are flexible and reusable circuits that can be easily reconfigured by the designer. One of the steps involved in the logic design with FPGA circuits is placement. In this step, the logic functions are assigned to specific cells of the circuit. In this paper we present a placement algorithm for FPGA circuits. In traditional min-cut based placement algorithm...

Field-Programmable Gate Arrays (FPGAs) are flexible circuits that can be (re)configured by the designer. The efficient use of these circuits requires complex CAD tools. One of the steps of the design process for FPGAs is represented by placement. In this paper we present a genetic algorithm for the FPGA placement problem, in particular for the Atmel FPGA circuits. Because of the limited routing...

FPGA placement and routing are still challenging problems. Given the increased diversity of logic and routing resources on FPGA chips, it seems appropriate to tackle the placement problem as a mapping between the nodes and edges in a circuit graph to compatible resources in the architecture graph. We explore utilizing graph isomorphism algorithms to perform FPGA placement. We use a hierarchical...

The traditional approach to FPGA clustering and CLB-level placement has been shown to yield significantly worse overall placement quality than approaches which allow BLEs to move during placement. In practice, however, modern FPGA architectures require computationally-expensive Design Rule Checks (DRC) which render BLE-level placement impractical. This thesis research addresses this problem by ...