In current day microprocessors, exponentially increasing power densities, leakage, cooling costs, and reliability concerns have resulted in temperature becoming a first class design constraint like performance and power. Hence, virtually every high performance microprocessor uses a combination of an elaborate thermal package and some form of Dynamic Thermal Management (DTM) scheme that adaptive...

On-chip implementation of multiprocessor systems requires the planarization of the interconnect network onto the silicon floorplan. Manual floorplanning approaches will become increasingly more difficult and ineffective as multiprocessor complexity increases. Compared with traditional ASIC architectures, multiprocessors have homogeneous processing elements and regular network topologies. Theref...

---------------------------------------------------------------------***--------------------------------------------------------------------Abstract Floorplanning is an important problem in very large scale integrated-circuit (VLSI) design automation as it determines the performance, size, yield, and reliability of VLSI chips. From the computational point of view, VLSI floorplanning is an NP-ha...

In VLSI circuit design, physical design is one of the main steps in placing into chip area. Floorplanning a crucial step IC which generates blueprint for placement modules chip. A floorplanning accepts netlist as its input, given by circuit-partitioning design. The optimal placements modules. contains modules’ dimensions, size, and interconnect information. During floorplan generation, area, wi...

Floorplan representation is a fundamental issue in designing a VLSI floorplanning algorithm as the representation has a great impact on the feasibility and complexity of floorplan designs. This survey paper gives an up-to-date account on various nonslicing floorplan representations in VLSI floorplanning.

Floorplanning is a crucial phase in VLSI Physical Design. The subsequent placement and routing of the cells/modules are coupled very closely with the quality of the floorplan. A widely used technique for floorplanning is Simulated Annealing. It gives very good floorplanning results but has major limitation in terms of running time. For more than tens of modules Simulated Annealing is not practi...

Low Power Design has become a significant requirement when the CMOS technology entered the nanometer era. Multiple-Supply Voltage (MSV) is a popular and effective method for both dynamic and static power reduction while maintaining performance. Level shifters may cause area and Interconnect Length Overhead(ILO), and should be considered at both floorplanning and post-floorplanning stages. In th...

Floorplanning is an early phase in chip planning. It provides information on approximate area, delay, power, and other performance measures. Careful floorplanning is thus of extreme importance. In many applications while a good floorplan is needed, not all modules’ information are available, or even worse, part of the provided information is inaccurate. Floorplanning with uncertainty is the pro...

In deep submicron VLSI designs, cross capacitance between adjacent wires becomes the dominant factor in determining chip performance and power consumption. Consequently, traditional floorplanning algorithms, which typically optimize for die area and ignore wire congestion, become inadequate in deep submicron era. Based on a stochastic congestion model, we propose a floorplanning algorithm that ...

for Interconnect-Driven Floorplanning Zheng Xu , Song Chen , Takeshi Yoshimura 1 and Yong Fang 2 1 Graduate School of Information, Production and Systems, Waseda University, Japan Hibikino2-6-317, Wakamatsu, Kitakyushu, Fukuoka 808-0135, Japan 2 School of Communication and Information Engineering, Shanghai University, China Yanchang Road 149, Shanghai 200072, China E-mail: [email protected]....