Elmore delay has been widely used to estimate the interconnect delays in the performance-driven synthesis and layout of VLSI routing topologies. For typical RLC interconnections, Elmore delay can deviate signiicantly (by up to 33% or more) from SPICE-computed delay, since it is independent of inductance. Here, we develop an analytical delay model based on rst and second moments to incorporate i...

This work presents a Steiner tree construction procedure, Maximum delay violation Elmore routing tree, to meet specified sink arrival time constraints. It is shown that the optimal tree requires the use of non-Hanan points. The procedure works in two phases: a minimum-delay Steiner Elmore routing tree is first constructed using a minor variant of the Steiner Elmore routing tree procedure, after...

In this paper, we consider non-uniform wire-sizing. Given a wire segment of length L, let f(x) be the width of the wire at position x, 0 x L. We show that the optimal wire-sizing function that minimizes the Elmore delay through the wire is f(x) = ae ?bx , where a > 0 and b > 0 are constants that can be computed in O(1) time. In the case where lower bound (L > 0) and upper bound (U > 0) on the w...

Recently Lillis, et al. presented an elegant dynamic programming approach to RC interconnect delay optimization through driver sizing, repeater insertion, and, wire sizing which employs the Elmore delay model for RC delay estimation and a crude repeater delay model. This approach, however, ignores an equally important aspect of interconnect optimization: transition time constraints at the sinks...

Recent years have seen significant research in finding closed form expressions for the delay of the RLC interconnect which improves upon the Elmore delay model. However, several of these formulae assume a step excitation. But in practice, the input waveform does have a non zero time of flight. There are few works reported so far which do consider the ramp inputs but lacks in the explicit nature...

We develop an analytical delay model based on rst and second moments to incorporate inductance e ects into the delay estimate for interconnection lines. Delay estimates using our analytical model are within 15% of SPICE-computed delay across a wide range of interconnect parameter values. We also extend our delay model for estimation of source-sink delays in arbitrary interconnect trees. For the...

We address the eecient construction of interconnection trees with near-optimal delay properties. Our study begins from rst principles: we consider the accuracy and delity of easily-computed delay models (speciically, Elmore delay) with respect to the delay values computed from detailed simulation of underlying physical phenomena (e.g., SPICE simulator output). Our studies show that minimization...

This paper compares two celebrated studies New York City Community School District 2 (Elmore & Burney, 1999), and Good to Great (Collins, 2001) which examined sustained success in American corporations to the case of a single high performing school district. The question of interest concerns how school districts achieve and maintain high performance. The study focuses on five central issues fro...