A 0.5–5 GHz wide-range multiphase delay-locked loop (MDLL) with a calibrated charge pump is presented. A multiperiod-locked technique is used to enhance the input frequency range of a MDLL and avoid the harmonic-locked problem. The charge pump current is also calibrated to reduce the static phase error. This MDLL has been fabricated in 0.13m CMOS process. The measured root-mean-square and peak-...

The traditional analog signal processing is expected to progressively substituted by the processing times of the digital domain in the VLSI .Within this novel paradigm ,digitally controlled delay lines should play the vital role in the digital-toanalog converters ,and in analog intensive circuits. From a practical point of view, nowadays, DCDL is a key block in the many applications like All Di...

An improved architecture for all digital Delay Locked Loop (ADDLL) had been developed and implemented for several applications and design methodologies. In most cases it can be based on standard cells only. Several techniques are used to minimize the jitter, achieving less than 40pS (peak) for 0.13μ technology. The frequency range is very wide, exceeding 500MHz. For 0.13μ core, the area is 0.01...

A high-speed triangular-modulated spread-spectrum clock generator using a fractional phase-locked loop is presented. The fractional division is implemented by a nested fractional topology, which is constructed from a dual-modulus divide-by-(N–1/16)/N divider to divide the VCO outputs as a first division period and a fractional control circuit to establish a second division period to cause the o...

In this paper a new phase-frequency detector is proposed using transmission gates which can detect phase difference less than 500ps. In other word, the proposed Phase-frequency Detector (PFD) can work in frequencies higher than 1.7 GHz, whereas a conventional PFD operates at frequencies less than 1.1 GHz. This new architecture is designed in TSMC 0.13um CMOS Technology. Also, the proposed PFD a...

In this work, we present a 200 MHz to 1.6 GHz digital delay-locked loop (DLL) for per-pin deskew applications. The proposed phase shifters apply linear and scalable circuit architecture for the pin-to-pin delay mismatch of parallel I/O pins. The proposed phase detector with a detection window and the proposed consecutive phase decision method reduce the sensitivity to reference clock jitter. A ...

In this paper, a multipath mitigation tracking system is presented for static GPS applications. It is comprised of four function blocks, those being (1) adaptive path estimator (APE), (2) multipath interference reproducer (MPIR), (3) Rake-based delay locked loop (RB-DLL), and (4) Rake-based phase locked loop (RB-PLL). Only the short delay condition with delay less than 1.5 PN chip is considered...

The duty-cycle of a clock, within the VLSI IC, is liable to be changed when the clock passes through several buffer stages in the multistage clock buffer design. The pulse-width may be changed due to unbalance of the p and n MOS transistors in the long CMOS buffer. This paper describes a delay locked loop with double edge synchronization mainly used in a clock alignment process. SPICE simulatio...

This paper describes an oversampling data recovery circuit composed of an analog delay locked loop and a digital decision logic. The novel oversampling technique is based on the delay locked loop circuit locked to multiple clock periods rather than a single clock period, which generates the timing resolution less than the gate delay of the delay chain. The digital logic for data recovery was im...