This paper introduces three popular analog-to-digital converter (ADC) architectures to readers: the flash ADC, the multi-step flash ADC, and the pipeline ADC. The fundamental operating principles of these three architectures are described. The specific topic of interest of this paper is methods of improving ADC accuracy. For the flash ADC, the concept of 2X interpolation to increase ADC resolut...

A simple mismatch-shaping scheme is proposed for a two-capacitor DAC. Unlike in other mismatchshaping systems, the shaped error is generated by direct ltering of a well-de ned bounded signal, which can be generated as white noise. The operation is closely related to a speci c digital interpolation lter, but arbitrary properties of the overall interpolation characteristic can be assured. Simulat...

The paper describes a case study of new 12-bit low power switched-capacitor (SC) ADC for portable applications. The paper is focused on block design of ADC and its behavioural modelling regarding low power consumption. It is reached by Op-Amp sharing technique utilisation. The basic block topology design is outlined too. The cancellation techniques for avoiding of capacitor mismatch, clock feed...

The paper describes design requirements of a basic stage (called MDAC Multiplying Digital-toAnalog Converter) of a pipelined ADC. There exist error sources such as finite DC gain of opamp, capacitor mismatch, thermal noise, etc., arising when the switched capacitor (SC) technique and CMOS technology are used. These non-idealities are explained and their influences on overall parameters of a pip...

In this paper an analytic approach to estimate the nonlinearity of radix-4 pipelined analog-to-digital converters due to the circuit non-idealities is presented. Output voltage of each stage is modeled as sum of the ideal output voltage and non-ideal output voltage (error voltage), in which non-ideal output voltage is created by capacitor mismatch, comparator offset, input offset, and finite ga...

The “Split ADC” architecture enables fully digital calibration and correction of nonlinearity errors due to capacitor mismatch in a Successive Approximation (SAR) ADC. The die area of a single ADC design is split into two independent halves, each converting the same input signal. Total area and power is unchanged, resulting in minimal increase in analog complexity. For each conversion, the half...

Abstract Capacitor mismatch problem due to process variation causes weight error, which deteriorates the linearity of SAR ADC. In this paper, a novel calibration scheme based on genetic algorithm(GA) combined with radix‐less‐than‐2 ADC is proposed extract error caused by capacitor mismatch. This foreground and no extra injections are added. The GA‐based simulated 40 nm CMOS technology. After ca...

During the past decade, SAR ADCs have enjoyed increasing prominence due to their inherently scaling-friendly architecture. Several recent SAR ADC innovations focus on decreasing power consumption, mitigating thermal noise, and improving bandwidth, however most of those using non-hybrid architectures are limited to moderate (8-10 bit) resolution. Assuming a nearly rail-to-rail dynamic range, com...