INSTRUCTIONS The diameter of silicon wafer becomes larger in order to increase the number of chips per one wafer. For such a larger diameter silicon ingot is mainly sliced by using multi-wire method, in which a long thin wire is used with slurry. In this method, several hundreds of wafers could be sliced at the same time. However there are still problems remained, such as large cracks, slurry t...

A cross-sectional survey of semiconductor factories was conducted to identify the ergonomic risk factors in the work processes, the prevalence of body pain among workers, and the relationship between body pain and work processes. A total of 906 women semiconductor workers took part in the study. In wafer preparation and polishing, a combination of lifting weights and prolonged standing might ha...

The influence of a SiNx coating of a Si wafer on sheet resistance (RSh) of a neighbouring wafer during POCl3 diffusion process is investigated. Wafers facing the SiNx layer of the neighboring wafer in the next slot of the quartz boat show a lower RSh compared to those facing a bare Si wafer, e.g. a reduction from 61 Ω/sq to 52 Ω/sq and a thicker PSG layer are determined. The active doping profi...

The dynamics of ions traversing sheaths in low temperature plasmas are important to the formation of the ion energy distribution incident onto surfaces during microelectronics fabrication. Ion dynamics have been measured using laser-induced fluorescence (LIF) in the sheath above a 30 cm diameter, 2.2 MHz-biased silicon wafer in a commercial inductively coupled plasma processing reactor. The vel...

Zero-level packaging technology ensures dicing and handling compatibility of the MEMS device along with low cost by encapsulating the MEMS components using wafer level processing. It is also essential for providing the MEMS with a controlled ambient in a cost-effective way. In order to be compatible with a broad range of MEMS processes, IMEC developed sealing methods with a low temperature budg...

The nature of the scattering pattern for silicon 004 wafer is described. At incidence angles (ω) set close to the expected diffraction condition of ω = θh`k`l` αhkl,h`k`l` (hkl are the planes parallel to the wafer surface and αhkl,h`k`l` is the interfacial angle between hkl and another set of diffracting planes h’k’l’), an anomalous kind of scattering has been observed. There is a broad weak fe...

We present a new model for dishing and erosion during chemical-mechanical planarization. According to this model, dishing and erosion is controlled by the local pressure distribution between features on the wafer and the polishing pad. The model uses a contact mechanics analysis based on the work by Greenwood to evaluate the pressure distribution taking into account the compliance of the pad as...

Wafer and die level uniformity effects in Deep Reactive Ion Etching (DRIE) are quantitatively modeled and characterized. A two-level etching model has been developed to predict non-uniformities in high-speed rotating microstructures. The separation of wafer level and die level effects is achieved by sequentially etching wafers with uniformly distributed holes. The wafer level loadings range fro...

cross-wafer standard deviation of Jc was typically ~ 5% for anodized wafers but was ≥15% for unanodized wafers (Figure 6). A low variation in Jc results in a higher yield of device chips per wafer with the desired current density. As a result of the improved cross-wafer distribution, the cross-chip uniformity is greatly improved as well; typically < 1% for anodized chips. Low cross-chip Jc vari...