Engineering Change Order or ECO phase is always challenging for any family of chip design. High Performance Microprocessors are largest and most complex overall design within Semiconductor Industry as a whole. To add further, there are additional design and methodology challenge related to bleeding edge of process nodes. Hence, current and future microprocessor design requires a set of well pla...

The VLSI placement problem is to place objects into a fixed die such that there are no overlaps among objects and some cost metrics (wire length, routability) are optimized. The nature of multiple objects and incremental design process for modern VLSI design demands Advanced Incremental Placement Techniques. Incremental placement changes either the wire length or the Placement Density of an exi...

Applications of Metric Embedding to Regular IC Optimization Ph. D. Dissertation Padmini Gopalakrishnan Department of Electrical and Computer Engineering Carnegie Mellon University Prof. Lawrence T. Pileggi, Chair In digital IC design methodologies, the design netlist is typically modeled as a graph or hypergraph, and information about its structure or topology is often used in optimization. Oft...

Serkan Askar Ma iej Ciesielski Department of Ele tri al & Computer Engineering University of Massa husetts, Amherst, MA 01003 fsaskar, iesielg e s.umass.edu Abstra t|This paper addresses the problem of layout design automation of datapath ells. We present a novel approa h to transistor pla ement problem for ustom datapath designs and demonstrate that it an be applied to pra ti al designs. Our a...

3D-ICs promise to reduce wire-delays, but non-idealities threaten to diminish the benefit. This paper presents an analysis of the performance improvement of a standard-cell implementation of an FFT when designed for the three-tier process from MIT Lincoln Labs. The methodology is presented, along with analyses of delay, routing congestion, and heat. The methodology uses commercial 2D CAD tools ...

Today’s designs have grown in size and complexity by orders of magnitude in comparison to common designs of only a few years ago. FPGAs have also grown in size and density, with 100k-gate FPGAs now available. Because of this growth in FPGA density, designs that previously required an ASIC implementation may now be targeted to an FPGA. However, schematic based design is no longer the ideal metho...

Current network access protocol stacks consist of a number of layers and components that are only loosely aware of each other. While this provides flexibility, it also results in a number of limitations, including high signalling latency due to duplicated tasks at multiple layers, security vulnerabilities, and deployment problems when new components and protocols are added. Most of currently on...

Future requirements for design technology are always uncertain due to changes in process technology, system implementation platforms, and applications markets. To correctly identify the design technology need, and to deliver this technology at the right time, the design technology community – commercial vendors, captive CAD organizations, and academic researchers – must focus on improving desig...