This paper addresses to enhance the stability of8T SRAM bitcell by lowering its leakage power. Scaling down of process parameters such as supply voltage affects the Read ability and Write stability of the cell. As number of transistors on chip increases power dissipation also increases and as a result of this stability of the cell gets affected. This paper aims at reducing the leakage power and...

This paper describes cryogenic broadband amplifier with very low noise for the frequency band 1.5-4.5 GHz. At 15 K the twostage InP-based amplifier has a gain of 28+/-2 dB dB and a noise temperature below 5 K. For a narrower band of 2-4 GHz at 15 K the measured gain is 30.0+/-0.8 dB and noise temperature is 1.5 K. The total DC power consumption of the amplifier is 6.8 mW. A lattice matched stru...

When liposomes are subjected to dehydration or freeze-thawing, vesicle fusion and/or leakage of vesicle contents can occur. The disaccharide, trehalose and the cryoprotectant, glycerol, are known to protect vesicle integrity during dehydration and freezing respectively. Here we examine their protective abilities as a function of vesicle size and lipid composition. It is shown that fatty acyl co...

Leakage is one of the most important reasons for failure hydraulic systems. The accurate positioning leakage great significance to ensure safe and reliable operation For early stage leakage, pressure circuit does not change obviously therefore cannot be monitored by sensors. Meanwhile, changes frequently due influence load state switch, which further reduces accuracy localization. In work, a no...

We investigate the effect of legal risk on private information spillover from syndicated loan borrowers to equity markets. find evidence that is consistent with leakage provided institutional investors in monthly reports. expect insiders avoid adverse consequences noise trading by timing trades closely before public announcements. Consistent this expectation, during a period low risk, we observ...

We report on a 3.3V12.5V compatible, 1.5V high performance dense CMOS SRAM technology utilizing a 2.74 um2 6-T Bitcell. This 0.18pm CMOS process with a nominal 0.13pm gate poly and a 30A gate oxide utilizes aggressive interwell isolation, enhanced self-aligned local interconnect, low-K interlevel dielectric, and scaled copper metalization. In addition, the technology allows for low leakage, hig...