In this paper we propose two buffer circuits for footed domino logic circuit. It minimizes redundant switching at the output node. These circuits prevent propagation of precharge pulse to the output node during precharge phase which saves power consumption. Simulation is done using 0.18μm CMOS technology. We have calculated the power consumption, delay and power delay product of proposed circui...

The purpose of this project is to lower the power consumption by reducing the operating voltage of a 32-bit adder, implemented with TSMC035 technology. The delay and power dissipation of the circuit at different voltages were studied and based on the power delay product an optimal voltage of operation was chosen. A level converter circuit was designed, in order to make the circuit compatible wi...

In this paper, a low power single edge triggered D flip-flop is presented by using True Single Phase Clocked technique (TSPC). The proposed design overcomes the problem of race condition at the output caused by clock pulses. This technique uses single phase clock pulse and it has less number of transistors. All the circuits are designed and simulated using Cadence® Virtuoso® Design Environment ...

In this paper we analyze the effects of transient faults (TFs) affecting the internal nodes of conventional latch structures and we propose a new latch design which allows to tolerate such faults. In particular, we show that standard latches using back-to-back inverters for their positive feedback are very susceptible to glitches on their internal nodes. We propose a new latch that is hardened ...

A new 3-Input XOR gate based upon the pass transistor design methodology for lowvoltage, low-voltage high-speed applications is proposed. Five existed circuits are compared with the new proposed gate. It is shown that the proposed new circuit has at least 50% improvement in power-delay product than the CPL structure and than the CMOS structure. Moreover, the proposed new circuit could also be o...

Abstract This paper proposes a novel architecture of excess-1 adder-based Carry Select Adder (M2CSA) using single leaf cell i.e., 2–1 Multiplexer. M2CSA is designed new type Excess-1 block. The block in distinct way multiplexers. architectures the proposed carry select adder and its internal blocks are completely when compared to existing adders. 4-, 8-, 16-, 32-, 64-bit M2CSAs use multiplexer ...

This paper presents a high-speed and high-performance CNFET-based Full Adder cell for low-voltage applications. The proposed Full Adder cell is composed of two separate modules with identical hardware configurations which generate the Sum and Cout signals in a parallel manner. The great advantage of the proposed structure is its very short critical path which is composed of only two CNT pass-tr...

As the in semiconductor industries progress by following Moore’s law faithfully from last five decades, and integrating more transistors along with functional circuits on a single chip periodically with every coming process technology. However, this progress help in rapid run towards tiny, circuit design high speed and economical VLSI (Very Large Scale of Integration) circuits has added to exce...

Power efficiency is becoming an increasingly important design aspect for FPGAs. Recently it has been shown that well-known power minimization techniques in the ASICs such as creating supply voltage (Vdd) scalable islands of different granularity can be applied to FPGAs. However, the discrete routing architecture of FPGAs amplifies any constraint imposed on the placement stage. In this work, we ...