A major component of computer chip design is creating an optimal physical layout of a netlist, i.e., determining where to place the functional elements and how to route the wires connecting them when manufacturing a chip. Because of its basic structure, the overall problem of netlist layout contains many questions that lend themselves to graph theoretical modeling and analysis. We will describe...

We investigate the effect of substrate thickness on the transmission bandwidth of on-chip terahertz-frequency-range planar Goubau lines both experimentally and theoretically. The bandwidth and frequency resolution are improved through substrate thinning and geometry modifications (reducing reflections arising from the THz photoconductive generators and detectors). We demonstrate that the enhanc...

objectives: human immunodeficiency virus type 1 is the causative agent of acquired immunodeficiency syndrome “aids” in human and demonstration of hiv-1 genome in samples is accepted as evidence of infection. transmission of infection during window period in blood transfusion settings is a world wide concern. also there is a need for a rapid, sensitive and accurate technique to detect hiv-1 infe...

Thickness is a commonly used parameter in product design and manufacture. Its intuitive definition as the smallest dimension of a cross-section or the minimum distance between two opposite surfaces is ambiguous for intricate solids, and there is very little reported work in automatic computation of thickness. We present three generic definitions of thickness: interior thickness of points inside...

The processor and its packaging are idealized as depicted in Figure 1. ATMI models two layers of different materials. Typically, layer 1 is silicon and layer 2 is metal. Both layers have horizontal dimensions L× L, with L the width of the metal layer (or the square root of its area). That is, ATMI assumes a large silicon chip, which neglects the impact of chip edges. The interface material betw...

We first present a unged formulation to three problems in VLSI physical design: Layout compaction, Wire balancing and Integrated layout compaction and wire balancing problems. The aim of layout compaction is to achieve minimum chip width. Whereas wire balancing seeks to achieve minimum total wire length, integrated layout compaction and wire balancing seeks to minimize wire length maintaining t...

applied for preventative treatment of an existing road or to overlay low-trafficked roads. The thickness the superstructure a chip seal pavement is directly related bearing capacity sub-grade soil. soil represented by Resilient Modulus (MR) design layers. This study has focused on effect and cost superstructures seals. In addition, linear regression analysis was performed investigate relationsh...

Wireless network on chip (WiNoC) is one of the promising on-chip interconnection networks for on-chip system architectures. In addition to wired links, these architectures also use wireless links. Using these wireless links makes packets reach destination nodes faster and with less power consumption. These wireless links are provided by wireless interfaces in wireless routers. The WiNoC archite...

We develop the helicity modulus as a criterion for superconducting order in the mixed phase of a fluctuating type II superconductor. We show that there is a duality relation between this helicity modulus and the superfluid density of a system of analog 2D bosons. We show that the vortex line lattice exhibits a perfect Meissner effect with respect to a shearing perturbation of the applied magnet...