Variations in sampling time, or sampling jitter, is a common industrial control problem. This paper investigates the performance of industrial PI and PID controllers in the presence of sampling jitter. The commonly employed controller performance assessment (CPA) benchmark index is used on a wide variety of industrial plant models to show that while the PI control is relatively immune to jitter...

This paper shows that, for a given power budget, a practical phase-locked loop (PLL)-based clock multiplier generates less jitter than a delay-locked loop (DLL) equivalent. This is due to the fact that the delay cells in a PLL ring-oscillator can consume more power per cell than their counterparts in the DLL. We can show that this effect is stronger than the notorious jitter accumulation effect...

OBJECTIVE To compare the jitter values in voluntarily activated (v-CNE) and stimulated (s-CNE) techniques for Extensor Digitorum Communis muscle using a disposable concentric needle electrode (CNE). Quantifying jitter using a CNE in conjunction with a stimulated technique has not been reported previously. METHODS Forty-one normal subjects were studied, 15 male and 26 female with a mean age of...

pump boosting circuit, one PLL with a charge pump boosting circuit and another one without a boosting circuit (the same as the conventional PLL) have been implemented in a 0 . 8 ~ CMOS technology. Fig. 3 shows the maximum frequency to which both PLLs can lock with a supply voltage change. The proposed PLL can be locked to 672MHz at 3.3V supply, which is 1.9 times the maximum frequency of the co...

By using adiabatic perturbation theory, we calculate the timing jitter generated by fluctuations in soliton amplitude, frequency, and position that are induced by the amplifiers noise in high-speed soliton communication systems. The analysis is applied to dispersion-tailored fibers which, in contrast with conventional constantdispersion fibers, allow ultrashort solitons (width , 10 ps) to propa...

Avoiding delay jitter is essential to achieve high throughput for TCP. In particular, delay spikes can cause spurious timeouts. Such timeouts force TCP into slow-start, which may reduce congestion window sizes drastically. Consequently, there may not always be data available for transmission on bottleneck links. For HS-DSCH, jitter can occur due to varying interference. Also, properties of the ...

Transmitting real-time voice over the Internet is a technological challenge. Variation in network characteristics introduces jitter to the propagating voice packets. Jitter hampers voice quality and makes the VoIP call uncomfortable to the user. Often buffers are used to store the received packets for a short time before playing them at equal spaced intervals to minimize jitter. Choosing optimu...

We propose a joint optimization framework for quality-of-service (QoS) routing with resource allocation in a generalized processor sharing (GPS) network. Our joint optimization framework provides a convenient way of maximizing the reliability or minimizing the jitter delay of paths. Data traffic is sensitive to droppage at buffers while it can tolerate jitter delay. On the other hand multimedia...

In this paper, we build a novel well-proved model for describing the combined error due to clock jitter and quantization noise on the performance of bandpass sigma delta (Σ∆) analog to digital converters (ADCs). The clock jitter is modeled as a timing variation of the sampling process which follows the characteristic of the Wiener process. Computer simulations as well as theoretical calculation...

This paper describes sampling clock jitter effects in digital-to-analog converters. A formula for the output error power due to sampling clock jitter for a sinusoidal input is derived and verified by numerical simulations, and its spectrum characteristics is shown. Also its effects on DAC SNR is clarified by numerical simulation as follows: (i) When the total noise power outside as well as insi...