Sub-quarter micron MOSFET’s and ring oscillators with 2.5–6 nm physical gate oxide thicknesses have been studied at supply voltages of 1.5–3.3 V. Idsat can be accurately predicted from a universal mobility model and a current model considering velocity saturation and parasitic series resistance. Gate delay and the optimal gate oxide thickness were modeled and predicted. Optimal gate oxide thick...

Assigning gate supply voltage and transistor threshold voltages to a range of discrete values is a combinatorial problem. The optimization computational difficulty grows exponentially with the netlist size. Whereas, if the range of values is continuous, we show that the global optimum can be found in polynomial time. We show that posynomials can model variable supply and threshold voltages, wit...

This paper studies the Ethernet Passive Optical Network (EPON) with gated-limited service. The transmission window (TW) is limited in this system to guaranteeing a bounded delay experienced by disciplined users, and to constrain malicious users from monopolizing the transmission channel. Thus, selecting an appropriate TW size is critical to the performance of EPON with gated-limited service dis...

We present a timing optimization algorithm based on the concept of gate duplication on the technologydecomposed network. We first examine the relationship between gate duplication and delay reduction, and then introduce the notion of duplication gain for selecting the good candidate gates to be duplicated. The objective is to obtain the maximum delay reduction with the minimum duplications. The...

| It has been shown earlier that, if we restrict to unate gate network (UGN) realizations, there exist universal test sets for boolean functions. Such a test set only depends on the function f , and checks any UGN realization of f for all multiple stuck-at faults and all robustly testable stuck-open faults. In this paper we prove that these universal test sets are much more powerful than implie...

This paper presents a gate sizing method which formulates minimum active area solutions under delay constraints. It is based on the logical effort delay model. Such minimization of transistor widths has direct impact on the power consumption and circuit area reduction. The explicit formulation of the method takes into account the maximum input capacitance, the output load to be driven, and the ...

For CMOS feature size of 65 nm and below, local (or intra-die or within-die) variations in transistor Vt contribute stochastic variation in logic delay that is a large percentage of the nominal delay. Moreover, when circuits are operated at low voltage (Vdd ≤ 0.5V), the standard deviation of gate delay becomes comparable to nominal delay, and the Probability Density Function (PDF) of the gate d...