The ability to protect critical cyber infrastructure remains a multi-faceted problem facing both the commercial sector and the federal government. Hardware intellectual property (IP) embedded within application-specific integrated circuits and programmable logic devices are subject to adversarial analysis in the form of subversion, piracy, and reverse engineering. We consider the effect of tran...

As integrated circuits technology sizes shrink, variability in process parameters, such as the threshold voltage, are expected to increase and become worse under low supply voltage (VDD). Circuit parameters, such as the propagation delay in logic gates and the resolution time from metastability in flipflops, will vary more. As a consequence, the synchronizer failure rate would be unpredictable....

Background and Objectives: Recently, photonic crystals have been considered as the basic structures for the realization of various optical devices for high speed optical communication. Methods: In this research, two dimensional photonic crystals are used for designing all optical logic gates. A photonic crystal structure with a triangular lattice is proposed for making NAND, XNOR, and OR optica...

A new current-source control technique is proposed to design a low-power high-speed multiplevalued current-mode (MVCM) integrated circuit in a low supply voltage. The use of a di erential logic circuit (DLC) with a pair of dual-rail inputs makes the input voltage swing small, which results in a high driving capability at a lower supply voltage, while having large static power dissipation. In th...

Dynamic logic style is used in high performance circuit designs because of its faster speed and lesser transistor requirement as compared to static CMOS logic style. Dynamic logic has inherent disadvantages like less noise immunity and high power consumption. In this paper we have proposed a novel circuit technique for implementing dynamic gate. The proposed circuit has very less power dissipat...

Circuit delays in MOS integrated circuits often need to be reduced to obtain faster response times, with a minimal area penalty. A typical MOS digital integrated circuit consists of multiple stages of combinational logic blocks that lie between latches, clocked by system clock signals. Delay reduction must ensure that the worst-case delay of the combinational blocks is such that valid signals r...

A new algorithm based on Input Vector Control (IVC) technique is proposed, which shifts logic gate of a circuit to its minimum leakage state, when device goes into its idle state. Leakage current in CMOS VLSI circuit has become a major constrain in a battery operated device for technology node below 90nm, as it drains the battery even when a circuit is in standby mode. Major concern is the leak...