As the number of system gates available on reconfigurable platforms increase beyond 10 million, the issue of the management of these resources and their sharing among many applications and users will become more of a concern. This paper identifies the fundamental services that must be provided by an operating system for reconfigurable computing and describes a prototype implementation. The pape...

Industrial designers and educators who plan to design microelectronic systems (e.g. hardware accelerators, co-processors, etc.) are increasingly capturing their designs using hardware description languages such as VHDL and Verilog. The designs are then most often synthesized into programmable logic components such as field-programmable gate arrays (FPGAs) offered by Xilinx, Altera, Actel and ot...

Design Automation for Streaming Systems by Eylon Caspi Doctor of Philosophy in Computer Science University of California, Berkeley Professor John Wawrzynek, Chair RTL design methodologies are struggling to meet the challenges of modern, large system design. Their reliance on manually timed design with fully exposed device resources is laborious, restricts reuse, and is increasingly ineffective ...

Circuit designers require Computer-Aided Design (CAD) tools when compiling designs into Field Programmable Gate Arrays (FPGAs) in order to achieve high quality results due to the complexity of the compilation tasks involved. Technology mapping is one critical step in the FPGA CAD flow. The final mapping result has significant impact on the subsequent steps of clustering, placement and routing, ...

Field programmable gate arrays (FPGAs) play many important roles, ranging from small glue logic replacement to System-onChip designs. Nevertheless, FPGA vendors can not accurately specify the energy consumption information of their products on the device data sheets because the energy consumption of FPGAs is strongly dependent on target circuit including resource utilization, logic partitioning...

The new Virtex device is for many people the solution to the long term problem of implementing random configurations on Digital Electronic devices as is required in the paradigm of Evolvable Hardware. It has previously been shown that Evolvable Hardware was possible on these devices and that it can be accomplished using partial reconfiguration to speed up the configuration process. Unfortunatel...

JBits(tm), the Xilinx Bitstream Interface is a set of Java (tm) classes which provide an Application Program Interface (API) into the Xilinx FPGA bitstream. This interface operates on either bitstreams generated by Xilinx design tools, or on bitstreams read back from actual hardware. This provides the capability of designing, modifying and dynamically modifying circuits in Xilinx XC4000 (tm) se...