In this paper we describe Frontier, an FPGA placement system that uses design macro-blocks in conjuction with a series of placement algorithms to achieve highly-routable and high-performance layouts quickly. In the first stage of design placement, a macro-based floorplanner is used to quickly identify an initial layout based on inter-macro connectivity. Next, an FPGA routability metric, previou...

A floorplan can be defined as a rectangular dissection of the floorplan region. Simple and tight asymptotic bounds on the number of floorplans for different dissection structures help us to evaluate the size of the solution space of different floorplan representation. They are also interesting theoretically. However, only loose bounds exist in the literature. In this paper, we derive tighter as...

High-performance design flows for FPGAs rely on automatic module generation [1] [2] [3] to quickly create fast and dense circuits. This structured circuit generation becomes even more crucial when FPGAs are used as compute elements in configurable computing machines (FCCM), instead of just implementing glue logic. Many research efforts on automatic compilation to FCCM targets include module gen...

With a fast rising productivity and even faster rising integration densities, i.e., designproductivity-gap, energy and power dissipation are critical topics in high level system design more than ever. Thermal aware system design, reliable power delivery, and the overall energy dissipation are only few crucial design properties. In this work we present a framework based on SystemC, enabling the ...

Field-Programmable Gate Arrays (FPGAs) are a recent kind of programmable logic device. They allow the implementation of integrated digital electronic circuits without requiring the complex optical, chemical and mechanical processes used in a conventional chip fabrication. FPGAs can be embedded in traditional system designflows to perform prototyping and emulation tasks. In addition, they also e...

As technology advances, design complexity is increasing and the circuit size is getting larger. To cope with the increasing design complexity, hierarchical design and IP modules are widely used. This trend makes module floorplanning/placement much more critical to the quality of a VLSI design than ever. A fundamental problem to floorplanning/placement lies in the representation of geometric rel...

Generate-and-test algorithms to solve con­ straint satisfaction problems are often ineffi­ cient , but can be constructed fairly easily by knowledge compilation techniques that con­ vert declarative problem knowledge and do­ main knowledge into a procedural format [Liew and Tong, 1987]. Current research is focus­ ing on methods to improve the efficiency of generate-and-test algorithms by comple...

Dynamic Partially Recon ̄guration (DPR) designs provide additional bene ̄ts compared to traditional FPGA application. However, due to the lack of support from automatic design tools in current design °ow, designers have to manually de ̄ne the dimensions and positions of Partially Recon ̄gurable Regions (PR Regions). The following ̄ne-grained placement for system modules is also limited because it ta...

| A new method of non-slicing oorplanning is proposed, which is based on the new representation for non-slicing oorplans proposed by [1], called bounded slicing grid(BSG) structure. We developed a new greedy algorithm based on the BSG structure, running in linear time, to select the alternative shape for each soft block so as to minimize the overall area for general oorplan, including non-slici...