This is the final report on the project entitled “Validation of AMSR snow depth on sea ice retrievals using an airborne pulse radar.” This is a collaborative project between the Center for Remote Sensing of Ice sheets (CReSIS) at the University of Kansas and NASA Goddard Space Flight Center (GSFC). We designed and developed ultrawideband radars for measuring thickness of snow over sea ice from ...

Previous investigations using flight testing and simulator studies have identified influence of vehicle flight speed and control system sensitivity on the bandwidth-phase delay criterion, not accounted for in the proposed new handling qualities criteria for rotorcraft (ADS-33C). In this paper, the impact of flight speed and control system sensitivity on handling qualities as depicted by the ban...

− Modular reconfigurable robots have shown the promises of great versatility and robustness; however programming locomotion gaits for hundreds of modules remains a challenge. In this paper we present a formal model for programming locomotion gaits in chain-type modular robots: Phase Automata. A phase automaton is an event-driven state automaton with an initial phase delay. The phase delay is no...

This paper proposes a novel architecture for ultra-tight integration of a High Sensitivity Global Positioning System (HSGPS) receiver with an Inertial Navigation System (INS), to address the issue of GPS tracking and positioning in degraded signal environments. By enhancing signal tracking loops in receivers through the use of optimal controllers/estimators and aiding from external source such ...

A line driver with configurable pre-emphasis is implemented in a 65 nm CMOS process. The utilizes three-tap feed-forward equalization (FFE) architecture. relative delays between the taps are selectable increments of 1/16th unit interval (UI) via an 8-stage delay-locked loop (DLL) and digital interpolator. It also possible to control output amplitude source impedance for each tap programmable ar...

In this paper, for the wireless network, wearable device, and Internet of Things (IoT) markets, a delay-locked loop (DLL) is used to implement accurate multiplication reference clock frequency various applications through an edge combiner (EC). A simpler structure more sensitive process, voltage, temperature (PVT), so DLL complements itself quickly in feedback system improves stability final ou...

In this paper we describe a novel Phase-Locked Loop (PLL) design for clock management applications. Such PLLs should operate over a wide range of frequencies, have tight constraints on jitter, power consumption and acquisition time, while being dynamically programmable by software means. In addition to the conventional fine tuning loop, the PLL has a coarse tuning loop to control the operating ...

This work concerns with the design and analysis of phase locked loops (PLLs). In the last decade a lot of works have been done about the analysis of PLLs. The phase locked loops are analyzed briefly, second order, third order, and fourth order. In practically the design of 1.3 GHz, 1.9V second order PLL is considered. SPICE simulation program results confirm the theory. Key-Words: Phase Locked ...

Substrate noise is the major source of performance limitation in mixed-signal integrated circuits. This paper studies substrate noise effects on the performance of delay-locked loops (DLLs). Due to their robust noise performance, the delay-lockedloops are widely used as clock generators of microprocessors. Although exploiting advanced circuit techniques reduces the timing jitter induced by the ...