CMOS micromachining processes are being increasingly used to fabricate integrated MEMS devices. Verification of such designs requires extraction from layout to mixed domain circuits and MEMS schematics for lumped parameter simulation. The higher etch hole density and multilayer interconnect in CMOS-MEMS designs results in a larger and more complex problem than in polysilicon MEMS. In addition, ...

As photonics moves from the single-device level toward large-scale, integrated, and complex systems on a chip, monitoring, control, and stabilization of the components become critical. We need to monitor a circuit non-invasively and apply a simple, fast, and robust feedback control. Here, we show non-invasive monitoring and feedback control of high-quality-factor silicon (Si) photonic resonator...

In this paper, we present a new gate-level approach to power and current simulation. We propose a symbolic model of complementary metal–oxide–semiconductor (CMOS) gates to capture the dependence of power consumption and current flows on input patterns and fan-in/fan-out conditions. Library elements are characterized once for all and their models are used during event-driven logic simulation to ...

In this paper a software design tool is presented that supports the designer in the development process of integrated MOS circuits. Here the general difficulty to find out the right parameter set of all devices in the circuit is split into small device-level tasks, so the designer is able to interactively compute proper W & L geometries of each single MOS-device. Starting with the common dilemm...

Thanks are due to my former colleagues of the low power group Gerd Jochens, Lars Kruse and Bernd Timmermann for inspiring discussions. who did numerous simulation runs and part of the implementation of GliPS and OCHATO. I would also like to take the opportunity to thank my colleague Till Winteler for reviewing the manuscript. Microelectronic products are the essential key for products of much h...

In this paper, we have proposed a new approach for optical failure analysis which employs a CMOS photon-emitting circuitry, consisting of a flipflop based on a sense amplifier and a photon-emitting device. This method can be used even with deepsubmicron processes where conventional optical failure analyses are difficult to use due to the low sensitivity in the near infrared (NIR) region of the ...

| Substrate crosstalk modeling and analysis techniques for a reliable SoC oriented mixed signal IC design are outlined. Substrate noise measurements by use of a source follower and a latched comparator clearly indicate that L di=dt and R i e ects on Vdd/Gnd wirings appear in the substrate. An experimental full chip substrate crosstalk veri cation system based on a macroscopic substrate noise mo...

In this paper an introduction to substrate noise in silicon on insulator (SOI) is given. Differences between substrate noise coupling in conventional bulk CMOS and SOI CMOS are discussed and analyzed by simulations. The efficiency of common substrate noise reduction methods are also analyzed. Simulation results show that the advantage of the substrate isolation in SOI is only valid up to a freq...

Hybrid reconfigurable logic circuits were fabricated by integrating memristor-based crossbars onto a foundry-built CMOS (complementary metal-oxide-semiconductor) platform using nanoimprint lithography, as well as materials and processes that were compatible with the CMOS. Titanium dioxide thin-film memristors served as the configuration bits and switches in a data routing network and were conne...