This paper reports a lateral CMOS-MEMS accelerometer with a measured noise floor of 1mG/ and a dynamic range larger than 13G. The accelerometer is fully compatible with conventional CMOS processes enabling the integration of most of the conditioning circuits. It is fabricated in a three metal layer 0.5μm CMOS process followed by a two-step dry etch release. An improved curl matching technique i...

This paper gives important features of CMOS and BiCMOS four-diodes direct coupled tuneable resistance. Circuit performances of three resistance topologies are explored and compared with the traditional CMOS tuneable transresistance designed from a one-stage operational transconductance amplifier (OTA). Simulations results have been realised using nominal parameters of the AMS 0.8μm CMOS and BiC...

In this paper, a new CMOS power amplifier that can operate at 70 GHz is designed and developed. The advantages of using 70 GHz at millimeter wave (mmW) band is the huge amount of bandwidth available for various purposes whether they are in the cellular industry or manufacture devices such as high bandwidth wireless LAN and low attenuation of bandwidth frequencies around 70 GHz bands comparing w...

A novel circuit topology for high-gain distributed amplifiers is presented in this study. Based on the conventional distributed architecture, the gain cells are realized by cascading cascode stages for gain enhancement. In addition, the stagger-tuning technique is extensively utilized in the design of the cascode stages as well as the cascaded stages, leading to significant improvement in terms...

--This paper describes the design and analysis of High gain and widest bandwidth operational amplifier for Analog to Digital conversion application. Different Techniques are used to enhance the output characteristics performance. These amplifiers demonstrate the highest frequency and widest bandwidth of operation for amplifier using reduced complexity algorithm. This paper presents an improved ...

This paper discusses the use of a low gain amplifier and a passive switched-capacitor (SC) network to enable the SC integrator function. The method is applied to a deltasigma modulator to achieve high resolution as proved by the 65-nm CMOS technology test vehicle. Compared with the conventional operational amplifier (op-amp)-based SC integrator, this solution utilizes a low-gain open-loop ampli...

IIn this paper, a tunable single-amplifier biquadratic lowpass filter is presented. It consists of one balanced low-gain current amplifier and a second-order MOSFET-C feedback network. The filter was integrated in a double-poly 0.6 pm CMOS process and operates from a 3.3 V power supply. The pole frequency is tunable from 15.2 to 17.2 MHz, the pole Q is 3, the spurious-free dynamic range is at l...

This paper presents a current re-use quadrature front end receiver architecture for ISM Band. The proposed architecture is a stacked QLMV cell which consists of a low-noise amplifier (LNA), mixer and voltage-controlled oscillator (VCO), which feeds into the intermediate frequency (IF) load. The LNA is a common source amplifier with Ls source degeneration, a double-balanced Gilbert cell mixer an...

As per the Moore’s law, there is an extreme increase in number of on chip devices, this increase in chip density results in power dissipation and thus the power utilization is unsatisfactory. So to avoid this problem the concept of Low Power system arises. As a part of microelectronics, it has been proposed to make the choice of minute circuit with attraction added by use of MOS cells. Since we...