In this paper, the impact of timing jitter in direct sequence ultra wideband (DS-UWB) system is investigated over multipath fading channel. Also, a novel hybrid direct sequence multiband UWB (DS-MBUWB) system is proposed to mitigate the impact of timing jitter. We analyze and compare the system performance for conventional DS-UWB and hybrid DS-MB-UWB with Rake receiver in the presence of timing...

Networked automation systems (NAS) are characterized by confluence of control, computation, communication and Information (CI) technologies. Design decisions of one domain are affected by the constraints posed by others. Reliable NAS design should address the requirements of the system, and simultaneously meet the constraints posed by other domains and this is called co-design in literature. Co...

As all-IP based mobile communications networks become a reality, it is important to understand how characteristics of these networks such as delay jitter can affect the overall performance of the system. We find that backbone network delay jitter can significantly influence the multiple access performance of an all-IP mobile communications system. To compensate for this, we introduce an adaptiv...

Multigigahertz flash ADC is limited by sampling clock timing jitter. Since it is used in high frequency applications it is essential to remove jitter effects which will reduce the efficiency of ADC. This paper describes the effect of clock transition time on the spurious free dynamic range of a CMOS sample and hold circuit. To improve SFDR the effect of finite clock transition time of the signa...

| This paper presents a salient method to nd an optimal bandwidth for low noise phase-locked loop (PLL) applications by analyzing a discrete-time model of charge-pump PLLs based on ring oscillator VCOs. The analysis shows that the timing jitter of the PLL system depends on the jitter in the ring oscillator and an accumulation factor which is inversely proportional to the bandwidth of the PLL. F...

This paper describes a Built-In-Self-Test (BIST) circuit that tests the relative timing jitter of NRZ data and recovered clock of PLL-based CDR. Using the jitter information, the bit error rate and peak to peak jitter can be estimated. This BIST circuit doesn’t need a high resolution and high accuracy delay line to achieve high accuracy measurement. It depends on calibration and curve fitting a...

Bang-Bang clock and data recovery (BBCDR) circuits are hard nonlinear systems due to the nonlinearity introduced by the binary phase detector (BPD). The specification of the CDR frequency response is determined by jitter tolerance and jitter transfer. In this paper, jitter transfer and jitter tolerance of the second-order BBCDR are characterized by formulating the time domain waveforms. As a re...

Oscilloscopes have been used extensively to analyze the jitter performance of serial data links providing estimates (measurements) of total jitter as well as its “random” and “deterministic” parts. Higher speed serial data signals containing jitter from sources such as crosstalk and multi-Gaussian random noise can cause traditional oscilloscope-based methods to greatly over or under estimate th...

We investigate the high-frequency timing jitter spectral density of mode-locked fiber lasers in different mode-locked regimes. Quantum-noise-limited timing jitter spectra of mode-locked-regime-switchable Yb fiber lasers are measured up to the Nyquist frequency with sub-100-as resolution. The integrated rms timing jitter of soliton, stretched-pulse, and self-similar Yb fiber lasers is measured t...

An integrated 10-Gb/s clock and data recovery circuit incorporates a LC-tank voltage-controlled oscillator, a half-rate binary phase detector and charge pump. On the basis of R.C.Walker's second-order model, and in accordance with jitter tolerance and jitter transfer, the minimum stability factor are derived in a view to determine the value of Cz and Rz finally. After the circuit design is acco...