We report on ambipolar gate-defined quantum dots in silicon insulator nanowires fabricated using a customized complementary metal–oxide–semiconductor process. The ambipolarity was achieved by extending gate over an intrinsic channel to both highly doped n-type and p-type terminals. utilize the ability supply carrier reservoirs demonstrate reconfigurably define, with same electrodes, double eith...

In this work we present a gate sizing tool based on Geometric Programming. The optimization can be done targeting both, delay and power/area minimization. In order to qualify our approach, the ISCAS’85 benchmark circuits are mapped for 350nm and 45nm technologies using typical standard cell libraries. Next, the mapped circuit is sized using our tool and the result is comparated to the original ...

In classical switching theory it is usually assumed that asynchronous sequential circuits are operated in the fundamental mode. In this mode, a circuit is started in a stable state; then the inputs are changed to cause a transition to another stable state. The inputs are not allowed to change again until the entire circuit has stabilized. In contrast to this, delay-insensitive circuits -the cor...

This paper discusses a gate resizing method for performance enhancement based on statistical static timing analysis. The proposed method focuses on timing uncertainties caused by local random fluctuation. Our method aims to remove both over-design and under-design of a circuit, and realize highperformance and high-reliability LSI design. The effectiveness of our method is examined by 6 benchmar...

The field programmable gate-array (FPGA) has become an important technology in VLSI ASIC designs. Most existing algorithms for performance-driven technology mapping for Lookup-table (LUT) based FPGA designs are based on the unit-delay model. In this paper we study the technology mapping problem under arbitrary net-delay models. We show that if the net delay can be determined or estimated before...

We explore the dynamics of a Hodgkin-Huxley-type model for thermally sensitive neurons that exhibit intrinsic oscillatory activity. The model is modified to include a feedback loop that is represented by two parameters: the synaptic strength and the transmission delay time. We analyze the dynamics of the neuron depending on the temperature, the synaptic strength, and the delay time. We find par...

In this paper, the circuit performances such as circuit delay, RF characteristics and SRAM static noise margin are presented. These analyses are performed by threedimensional device simulation using Mixed-mode option. The benefit of circuit delay in scaling will be maintained by introducing new structure (SOI, multi-gate), material (silicide, metal gate) and strain effect. However, concerning w...

The performance of a code tracking loop for a spread spectrum signal can be severely deteriorated in the presence of an interference signal. The interference signal is modeled as a signal with the same code but with a different delay and carrier frequency. The variance of the tracking delay error is derived in terms of loop bandwidth, chip duration, the interference and signal power and bandpas...

We present a gate delay model of CMOS logic gates driving a CRC load for deep sub-micron technology. Our approach is to replace series-parallel connected MOSFETs to an equivalent MOSFET and calculate the output waveform by an analytically derived formula. We present a MOSFET drain current model improved from the -th power law MOSFET model to represent the characteristic of the equivalent invert...

Circuit-performance implications for double-gate MOSFET scaling in the sub-25 nm gate length regime are investigated. The optimal gate-to-source/drain overlap needed to maximize drive current is found to be different than that needed to minimize FO-4 inverter delay due to parasitic capacitances. It is concluded that the effective channel length must be slightly larger than the physical gate len...