A low dropout voltage regulator with small output voltage variations and the ability of wide load current range support is proposed in this paper. In this LDO structure, a recycling folded cascode operational transconductance amplifier is used as an error amplifier, which has high transconductance and therefore high power efficiency. The designed LDO is simulated in 0.18 μm CMOS standard techno...

Electrical Engineering (ABSTRACT) The conventional power factor correction circuit has a fixed output voltage. However, in some applications, a PFC circuit with a wide output voltage range is needed. A single phase power factor correction circuit with wide output voltage range is developed in this work. After a comparison of two main power stage candidates (Buck+Boost and Sepic) in terms of eff...

Analytic techniques for predicting onset of voltage collapse in power systems often rely upon identification of a saddle node bifurcation. While many authors acknowledge that the separation between voltage phenomena and phase angle phenomena is far from absolute, most recent works have viewed voltage variation as the more significant problem. The goal of the work presented here is to shift focu...

In this paper, we propose novel interface circuits using Dynamic Over-Driving (DOD) and Adaptive Sensing (AS) scheme for high speed and energyefficient interface on a chip. Our AS-receiver makes it possible to use very low swing because of its good noise immunity against the threshold voltage variations, and our DOD-driver reduces data transmission time even through heavy load capacitances. The...

Micro piezoelectric vibration generator with high energy density may provide infinite and continuous energy for wireless sensor network. In order to improve generating capacity under given dimension, aiming at external force and displacement incentive environment, mathematics model of piezoelectric cantilever generator generating capacity are established, and influence law of unimorph and bimor...

The performance of CMOS image sensors in a deep sub-micron CMOS process is limited by two factors: 1) The increasing pixel temporal noise floor dominated by the 1/f noise from the pixel source follower (SF) and 2) The decreasing pixel analog swing due to the supply voltage scaling. In this paper, we present the possibility of using a buried channel n-MOST as the in-pixel source follower to redu...

The bipolar nature of ESD pulses such as MM introduces failure mechanisms that cannot be reproduced by TLP/HBM. A lowered breakdown voltage due to dynamic avalanching was observed. The key issue is that carriers injected during the first swing remain in the device after the current switches polarity. A case study for high-voltage diodes is presented.