Referring to Figure 1, a system for using a PLL to generate higher frequencies than the input, the VCO oscillates at an angular frequency of ωO. A portion of this signal is fed back to the error detector, via a frequency divider with a ratio 1/N. This divided down frequency is fed to one input of the error detector. The other input in this example is a fixed reference signal. The error detector...

A large signal device model is developed for type-II InP/GaAsSb/InP devices that is based on the UIUC Type-I SDD model. The model accurately characterizes a balanced 480/420 GHz fT/fMAX device, and is used to design and simulate a 200 GHz static frequency divider.

Orthogonal frequency division multiplexing (OFDM) is an attractive technique to accomplish wired or wireless broadband communications. Since it has been adopted as the terrestrial digital-videobroadcasting standard in Europe, it has also subsequently been embedded into many broadband communication standards. Many techniques for frame timing and frequency synchronization of OFDM systems have bee...

In this paper, we propose a new frequency synchronization algorithm for orthogonal frequency division multiplexing (OFDM) systems requiring only one training symbol, based on a conventional method which requires two training symbols. While the timing synchronization is obtained by using the conventional method, the carrier frequency offset is efficiently estimated by the proposed method. It is ...

In this contribution, we investigate the effect of carrier phase errors on the performance of orthogonal frequency division multiplexing (OFDM) and multicarrier code-division multiple access (MC-CDMA). We show that OFDM and MC-CDMA have essentially the same sensitivities to carrier phase errors. A constant carrier phase offset yields no degradation of the system performance. We show that OFDM a...

This work describes the design of a double-precision radix-8 divider. Low-power techniques are applied in the design of the unit, and energy-delay tradeoffs considered. The energy dissipation in the divider can be reduced by up to 70% with respect to a standard implementation not optimized for energy, without penalizing the latency. The radix-8 divider is compared with one obtained by overlappi...

The paper presents a method for digital compensation of the ratio and phase angle errors resistive voltage divider. system consists separate electrical circuit divider, based on National Instruments (NI) PCI eXtension Instrumentation (PXI) PXI-5922 acquisition cards (DAQ). A novel approach to real-time is presented, using signal processing. algorithm Wiener filtering finite-impulse-response (FI...

A high accurate and low-voltage analog CMOS current divider which operates with a single power supply voltage is designed in 0.18µm CMOS standard technology. The proposed divider uses a differential amplifier and transistor in triode region in order to perform the division. The proposed divider is modeled with neural network while TLBO algorithm is used to optimize it. The proposed optimiza...