This paper examines the problems of symbol timing estimation and timing recovery for ultra wideband impulse radio signals. Two different approaches based on the maximum likelihood technique are investigated. The first approach is based on derivative matched filter and the second one takes advantage of the early-late technique. Furthermore, two non-coherent timing recovery circuits are proposed ...

We have implemented a four-tap adaptive lter in a continuous-time analog VLSI circuit. Since an ideal delay is impossible to implement in continuous-time hardware, we implemented the delay line as a cascade of low-pass lters (called the Gamma lter). Since many years of research in our lab has shown that the Gamma lter outperforms the delay line for a wide range of applications, the Gamma lter s...

After presenting results of recent impulse-noise measurements in customer premises, a proposal for a simplified statistical model for impulse noise is presented. The new model is intended to replace the deterministic single impulse, widely known as Cook Pulse, especially in the upcoming standards for SDSL and also maybe VDSL. In addition to the statistical model also herein, sample impulses are...

Under 500ps Yong-Bin Kim Tom Chen Department of Electrical Engineering Colorado State University Abstract This paper presents a variable delay line DLL circuit implemented in a 0.8 m CMOS technology. A phase detector and two charge pump circuits calibrate the delay per stage of the delay line using push-pull type clock synchronization scheme. The delay line can be programmed 6 to 18 stages. The...

In this paper, a thorough analysis of the jitter behavior of a Delay Locked Loop (DLL) based clock multiplying architecture is presented. The noise sources that are included in the analysis are the noise of the delay elements, the reference jitter and the noise of the Phase Frequency Detector and Charge Pump combination. It is shown that the effect of all noise sources on the output timing jitt...

A digital delay-locked-loop (DLL) suitable for generation of multiphase clocks in applications such as timeinterleaved and pipelined ADCs locks in a very wide (40X) frequency range. The DLL provides 12 uniformly delayed phases that are free of false harmonic locking. The digital control loop has two stages: a fast-locking coarse acquisition is achieved in four cycles using binary search; a fine...

We report on a tunable all-optical delay line for pulses with optical frequency within the Rb D 2 absorption line. Pulses of 10 ns duration are delayed in a 10 cm hot vapour cell by up to 40 ns where the transmission reduces to approximately 10%. Using an optical frequency between absorption components from different isotopes allows the delay to be increased or decreased by optical pumping with...

The lack of optical buffer is still one of the main problems that hinder the development of all optical network. The current works on this topic mainly focus on emulating optical buffers with fiber delay line (FDL). Recent advances have shown the feasibility of emulating many kinds of optical buffers, such as the First In First Out (FIFO) buffer, priority buffer, etc. The Last In First Out (LIF...

The optimum wire shape for minimum signal propagation delay across an line is shown to have a general exponential form. The line inductance makes exponential tapering more attractive for lines than for lines. For lines, optimum wire tapering achieves a higher reduction in the signal propagation delay as compared to uniform wire sizing. Wire tapering can reduce both the propagation delay and pow...

Akhilesh Tyagi Iowa State University Department of Computer Science Ames, Iowa 50011 E-mail: [email protected] Abstract. The extremely high data rates of optical computing technology (100 Mwords/s and upward) present unprecedented challenges in the dynamic memory design. An optical fiber loop used as a delay line is the best candidate for primary, dynamic memory at this time. However, it pos...