نتایج جستجو برای: buffer circuit

تعداد نتایج: 155743  

1997
S. Pullela R. Panda A. Dharchoudhury G. Vijayan D. Blaauw

We describe a fast (linear time) procedure to optimally size transistors in a chain of multi-input gates/stages. The fast sizing is used in a simultaneous sizing and restructuring optimization procedure, to accurately predict relative optimal performance of alternative circuit structures for a given total area. The idea extends the concept of optimally sizing a buffer chain[5], and uses taperin...

Journal: :Microelectronics Journal 2021

This work presents a 24 ?GHz integrated Phase-Locked Loop in 60 sliding-IF transceiver for IEEE 802.15.3c standard with low phase noise. For noise, varactor and MOM cap combination method is applied this PLL. The capacitor bank optimized to decrease the noise folding from circuit within method. analog PLL fabricated 65 ?nm CMOS technology of ?98.8 dBc/[email protected] ?MHz, reference spur ?62....

Journal: :Iowa Journal of Cultural Studies 1999

Journal: :Sustainability 2023

In this study, semiconductor oxide cuprite (Cu2O) and indium tin (ITO) heterojunction solar cells with without a 10 nm thick titanium (Ti) thin film as the buffer layer were fabricated characterized for comparison. The Cu2O was formed by low-cost electrodeposition, Ti ITO layers deposited on glass substrate sputtering. interfacial microstructures, surface topology, electrical photovoltaic prope...

پایان نامه :وزارت علوم، تحقیقات و فناوری - دانشگاه صنعتی امیرکبیر(پلی تکنیک تهران) - دانشکده مهندسی کامپیوتر 1386

با ادامه ی روند کوچک شدن ابعاد فناوری ساخت و نیز افزایش پیچیدگی طرح ها، مشکلاتی چون افت کیفیت تخمین اتصالات در سطوح بالای طراحی فیزیکی و افزایش امکان واگرایی روند طراحی شدت یافته اند. برآیند این مشکلات باعث شده که برآورده شدن محدودیت های موردنظر طراح مشکل تر شده و طراحان سخت افزار در بسیاری از شرایط مجبور باشند بخش هایی از روند طراحی را بارها و بارها با شرایط مختلف تکرار کنند تا محدودیت های مور...

پایان نامه :وزارت علوم، تحقیقات و فناوری - دانشگاه ارومیه 1387

چکیده ندارد.

Journal: :IEICE Electronics Express 2021

A novel power-efficient analog buffer at liquid helium temperature is proposed. The proposed circuit based on an input stage consisting of two complementary differential pairs to achieve rail-to-rail level tracking. Results simulation SMIC 0.18um CMOS technology show the high driving capability and low quiescent power consumption cryogenic temperature. Operating single 1.4 V supply, could a sle...

2014
Yan Shan Ang Lin-Yue Lanry Yung

Biomolecular interactions have important cellular implications, however, a simple method for the sensing of such proximal events is lacking in the current molecular toolbox. We designed a dynamic DNA circuit capable of recognizing targets in close proximity to initiate a pre-programmed signal transduction process resulting in localized signal amplification. The entire circuit was engineered to ...

2014
Nick K. H. Huang Li Jun Jiang

-The performance of IC interconnects has been stretched tremendously recently years by high speed integrated circuit systems. Even though S-parameters are popularly used for the characterization of IC interconnects, their modeling has to consider the existence of active devices, such as buffers and drivers. The I/O model is difficult to obtain due to the IP protection and limited information. I...

Journal: :caspian journal of enviromental sciences 0
al. et o. rafieyan*1, a. a. darvishsefat2, s. babaii1, a. mataji1 m. saeed sabaee

in the past 25 years, rising of the caspian sea level, part of a natural treat to the sea, has inundated and destroyed many buildings and arable lands and threatened many inhabitations in coastal areas. the main reason for these damages is that the law-setback has lost its efficiency and human activities have proceeded seaward. the goal of this study is to introduce a proper setback line for th...

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