Wafer-to-wafer process reproducibility during plasma etching often depends on the conditioning of the inside surfaces of the reactor. Passivation of reactor surfaces by plasma generated species, often called seasoning, can change the reactive sticking coefficients of radicals, thereby changing the composition of the radical and ion fluxes to the wafer. Ion bombardment of the walls may influence...

Abstract This study examines the impact of bonding sequence on contact resistance in hybrid a via-middle Cu though-silicon via (TSV) wafer. Hybrid was performed at room temperature surface-activated method using an ultrathin Si film. Comparative various sequences revealed that (a) cleaning target Si, TSV, and electrode wafers with Ar fast atom beam (FAB), (b) transferring wafer into another cha...

We have demonstrated a new PEDAL process to make sub-25 nm nanowires template across the entire Silicon (110) wafer suitable for wafer-scale nanoimprinting. The “PEDAL lift-off” has the ability to fabricate metal nanowires directly on the wafers without using nanoimprint techniques. The process involves defining the edge by etching a trench, patterned using conventional i-line lithography, and ...

The first step in integrated circuit (IC) fabrication is preparing the high purity single crystal Si wafer. This is the starting input to the fab. Typically, Si wafer refers to a single crystal of Si with a specific orientation, dopant type, and resistivity (determined by dopant concentration). Typically, Si (100) or Si (111) wafers are used. The numbers (100) and (111) refers to the orientatio...

We present a method for converting photoluminescence images into carrier lifetime images for siliconwafers with inhomogeneous lifetime distributions, such as multi-crystalline silicon wafers, based on a calibration factor extracted from a separate, homogeneous, mono-crystalline calibration wafer and simple optical modelling of the photoluminescence signal from both the calibrationwafer and the ...

Preparation procedures and thermionic emission properties of graphitic carbon nanofibres (GCNFs) supported on Si wafer or commercial carbon felt supports are reported. GCNF/native-oxide Si wafer, GCNF/oxidized Si wafer, GCNF/Ni-coated Si wafer and GCNF/carbon felt nanocomposites are obtained by growing GCNFs from growth catalyst nanoparticles supported on these supports. Narrow herringbone GCNF...

By combining nanosphere lithography with template stripping, silicon wafers were patterned with hexagonal arrays of nanowells or pillars. These silicon masters were then replicated in gold by metal evaporation, resulting in wafer-scale hexagonal gratings for plasmonic applications. In the nanosphere lithography step, two-dimensional colloidal crystals of 510 nm diameter polystyrene spheres were...

Three different types of carrier techniques have been investigated and developed: thermal release tapes, solvable thermoplastic glue layer and mobile electrostatic carrier. These carriers were applied for manufacture of ultra-thin RFID chips, 12 μm thin CMOS image sensors and to a new process sequence that enables the formation of solder balls at the front side of an already thinned device wafe...

Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regi...

A technology platform demonstrating wafer-level assembly of heterogeneous technologies based upon vertical wafer stacking is described. This platform offers the potential for low-cost assembly of various compound semiconductor circuits with silicon ICs for wide bandwidth optoelectronic and spaceconservative packaging applications. Process development results obtained to date are presented, and ...