This paper presents the architecture of the control chip for an Asynchronous Transfer Mode (ATM) chipset, used in a distributing banyan network. This chip, with 4 switch chips, forms a scaleable 16x16 switching element that runs at 155 MHz. It is larger and much more efficient than previous switching nodes. The architecture uses shared multibuffering, since it is less bandwidth limited than a s...

On-chip parasitic inductance inherent to the power supply rails has become significant in high speed digital circuits. Therefore, current surges result in voltage fluctuations within the power distribution networks, creating delay uncertainty. On-chip simultaneous switching noise should therefore be considered when estimating the propagation delay of a CMOS logic gate in high speed synchronous ...

Recently developed methods for power estimation have primarily focused on combinational logic. In this paper, we present a framework for the eecient and accurate estimation of average power dissipation in sequential circuits. Switching activity is the primary cause of power dissipation in CMOS circuits. Accurate switching activity estimation for sequential circuits is considerably more diicult ...

This paper presents a new quasi adiabatic logic family that uses a pair of complementary split-level sinusoidal power supply clocks for digital low power applications such as sensors. The proposed two phase clocked adiabatic static CMOS logic (2PASCL) circuit utilizes the principle of adiabatic switching and energy recovery. By removing the diode at the charging path, higher output amplitude is...

Computing technologies are currently based on the binary logic/number system, which is dependent simple and off switching mechanism of prevailing transistors. With exponential increase data processing storage needs, there a strong push to move higher radix system that can eradicate or lessen many limitations system. Anticipated saturation Moore’s law necessity information density speed in futur...

Modern CMOS based advanced digital circuits suffer unwanted switching transients referred as ‘hazard’, due to ununilateral propagation delays. The hazard in combinational circuit results from a single variable change when the output should not have been altered or manipulated. The hazardous behavior of the logic circuit often creates a glitch. The glitching effect is negligible in very small ci...

This work scrutinizes the implementation and performance analysis of novel self-timed asynchronous logic. These templates are based on a delay-insensitive (DI) logic paradigm known as NULL Convention Logic (NCL) that supports RTZ protocol, includes clock-free operation, dual-rail encoding and monotonic transitions. Potential benefits include inherent robustness, low power, reduced noise ratio, ...

MOS current mode logic (MCML) is an emerging logic family which is gaining attention due to its high speed of operation, robust performance and presence of mere switching noise as compared to the CMOS logic family. In this paper we have compared universal gates using MCML and conventional CMOS in terms of power and propagation delay at 16-nm Technology node. Comparative analysis shows that MCML...

A novel low power multiplication algorithm for reducing switching activity through operand decomposition is proposed. Our experimental results show 12% to 18% reduction in logic transitions in both array multipliers and tree multipliers of 32 bits and 64 bits. Similar results are obtained for dynamic power dissipation after logic synthesis. One additional logic gate is required on the critical ...

Latching optical switches and optical logic gates with AND and OR functionality are demonstrated for the first time by the monolithic integration of a vertical cavity lasers with depleted optical thyristor structure. The thyristors have a low threshold current of 0.65 mA and a high on/off contrast ratio of more than 50 dB. By simply changing a reference switching voltage, this single device ope...