نتایج جستجو برای: silicon wafer

تعداد نتایج: 100624  

Journal: :Journal of Lightwave Technology 2021

Silicon ring resonator-based devices, such as modulators, detectors, filters, and switches, play important roles in integrated photonic circuits for optical communication, high-performance computing, sensing applications. However, the high sensitivity to fabrication variations has limited their volume manufacturability commercial adoption. Here, we report a low-cost post-fabrication trimming me...

Journal: :Nano letters 2009
Koungmin Ryu Alexander Badmaev Chuan Wang Albert Lin Nishant Patil Lewis Gomez Akshay Kumar Subhasish Mitra H-S Philip Wong Chongwu Zhou

Massive aligned carbon nanotubes hold great potential but also face significant integration/assembly challenges for future beyond-silicon nanoelectronics. We report a wafer-scale processing of aligned nanotube devices and integrated circuits, including progress on essential technological components such as wafer-scale synthesis of aligned nanotubes, wafer-scale transfer of nanotubes to silicon ...

2011
M. Moreno

We have developed a new process to produce ultra-thin crystalline silicon films with thicknesses in the range of 0.1−1 μm on flexible substrates. A crystalline silicon wafer was cleaned by SiF4 plasma exposure and without breaking vacuum, an epitaxial film was grown from SiF4, H2 and Ar gas mixtures at low substrate temperature (Tsub ≈ 200 ◦C) in a standard RF PECVD reactor. We found that H2 di...

Journal: :Proceedings of the ... International Symposium on Microelectronics 2021

Abstract This study examines the impact of bonding sequence on contact resistance in hybrid a via-middle Cu though-silicon via (TSV) wafer. Hybrid was performed at room temperature surface-activated method using an ultrathin Si film. Comparative various sequences revealed that (a) cleaning target Si, TSV, and electrode wafers with Ar fast atom beam (FAB), (b) transferring wafer into another cha...

Journal: :Crystals 2022

Ingot multicrystalline silicon (Mc-Si) needs to be improved in quality and reduced cost compared with Czochralski monocrystalline silicon. A uniform dense quartz nucleation layer was obtained by the electrophoretic deposition of powder on surface wafer. The deposited wafer annealed at 600 °C for 1 h, one side glued crucible. During growth Mc-Si crystal, can play a role. results show that averag...

2011
Sarmishtha Ghoshal Abul AM Ansar Sufi O Raja Arpita Jana Nil R Bandyopadhyay Anjan K Dasgupta Mallar Ray

A uniformly distributed array of micro test tubes and microbeakers is formed on a p-type silicon substrate with tunable cross-section and distance of separation by anodic etching of the silicon wafer in N, N-dimethylformamide and hydrofluoric acid, which essentially leads to the formation of macroporous silicon templates. A reasonable control over the dimensions of the structures could be achie...

Journal: :international journal of nano dimension 0
s. amirtharajan nanoscience research lab, department of physics, vhnsn college (autonomous), virudhunagar, 626 001, india. p. jeyaprakash nanoscience research lab, department of physics, vhnsn college (autonomous), virudhunagar, 626 001, india. j. natarajan nanoscience research lab, department of physics, vhnsn college (autonomous), virudhunagar, 626 001, india. p. natarajan nanoscience research lab, department of physics, vhnsn college (autonomous), virudhunagar, 626 001, india.

porous silicon (ps) samples have been prepared by electrochemical anodization of p-type silicon wafer by varying hf concentrations in the electrolytic solution. the structural, surface morphological, optical and surface composition analysis of the prepared samples were done by x-ray diffraction (xrd), scanning electron microscopy (sem), photoluminescence (pl) and fourier transform infrared (fti...

2002
Sameer T. Shikalgar David Fronckowiak Edward A. MacNair

The importance of semiconductor wafer fabrication has been increasing steadily over the past decade. Wafer fabrication is the most technologically complex and capital intensive phase in semiconductor manufacturing. It involves the processing of wafers of silicon in order to build up layers and patterns of metal and wafer material. Many operations have to be performed in a clean room environment...

2017
C. Y. Yeh A. Y. Chang Y. J. Wang P. C. Chen H. H. Tsai Y. Z. Juang

This paper presents a monolithic three-axis accelerometer with wafer-level package by CMOS MEMS process. The compositions of the microstructure are selected from CMOS layers in order to suppress the in-plane and out-of-plane bending deflection caused by the residual stresses in multiple layers. A switched-capacitor sensing circuit with a trimming mechanism is used to amplify the capacitive sign...

2004
Wenhua Zhang Weibin Zhang Peter G. Hartwell

We present a single-mask single-crystal silicon (SCS) process for the fabrication of suspended MicroElectroMechanical devices (MEMS). This is a bulk micro-machining process that uses Deep Reactive Ion Etch (DeepRIE) of a silicon-on-insulator (SOI) substrate with highly doped device layer to fabricate movable single-crystal silicon MEMS structures, which can be electrically actuated without meta...

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