As classic CMOS based integrated circuits hit technology and performance walls, network-on-chip (NoC) and three dimensional integration have been evolved to provide sustainable solutions. Our current research is geared to contribute towards performance centric 3D nanosystem design with architecture and layout optimizations while reducing power dissipation. It has three key aspects. First, archi...

After placement, the routing process determines the precise paths for nets on the chip layout to interconnect the pins on the circuit blocks or pads at the chip boundary. These precise paths of nets must satisfy the design rules provided by chip foundries to ensure that the designs can be correctly manufactured. The most important objective of routing is to complete all the required connections...

The unabated silicon technology scaling makes design and manufacturing increasingly harder in nanometer VLSI. On one hand, major design objectives such as timing, power, and noise are often conflicting with each other in modern designs with multi-million gates, resulting in complex design closure. On the other hand, design closure no longer guarantees historical yield norm, requiring ever-chall...

This paper presents a breakthrough decomposition theorem on routing topology and its applications in the designing of universal switch blocks. A switch block of k sides and W terminals on each side is said to be universal (a (k, W )-USB) if it is routable for every set of 2-pin nets with channel density at most W . The optimum USB design problem is to design a (k, W )-USB with the minimum numbe...

Field-Programmable Gate Arrays (FPGAs) are a new type of user-programmable integrated circuits that supply designers with inexpensive, fast access to customized VLSI. A key component in the design of an FPGA is its routing architecture, which comprises the wiring segments and routing switches that interconnect the FPGA’s logic cells. Each of the user-programmable switches in an FPGA consumes si...

Advances of very large scale integration technologies present two challenges for routing problems: 1) the higher integration of transistors due to shrinking of featuring size and 2) the requirement for off-grid routing due to the variable-width variable-spacing design rules imposed by optimization techniques. In this paper, we present a multilayer gridless detailed routing system for deep submi...

In the context of physical synthesis, large-scale standard-cell placement algorithms must facilitate incremental changes to layout, both local and global. In particular, flexible gate sizing, net buffering and detail placement require a certain amount of unused space in every region of the die. The need for “local” whitespace is further emphasized by temperature and power-density limits as well...

Ultra-Fast Automatic Placement for FPGAs The demand for high-speed Field-Programmable Gate Array (FPGA) compilation tools has escalated for three reasons: first, as FPGA device capacity has grown, the computation time devoted to placement and routing of circuits has grown more dramatically than the available computer power. Second, there exists a subset of users who are willing to accept a redu...

Entitled: " Congestion Driven Clock Tree Routing with Via Minimization " and submitted in partial fulfillment of the requirements for the degree of Master of Applied Science Complies with the regulations of this University and meets the accepted standards with respect to originality and quality. Physical routability constraints such as legal location checking and excessive number of vias are us...