In this paper it has been demonstrated that a shielded channel made by varying the side gate length in silicon-on-nothing junctionless transistor not only improves short effect but also improve performance of CMOS circuits device. The proposed device dual stack silicon on nothing (SCDGSSONJLT) drain induced barrier lowering (DIBL), cut-off frequency and subthreshold slope are improved 20%, 39% ...

This paper describes the impression of low-k/high-k dielectric on performance Double Gate Junction less (DG-JL) MOSFET. An analytical model threshold voltage DG-JLFET has been presented. Poisson’s equation is solved using parabolic approximation to find out voltage. The effect high-k various parameters N-type explored. comparative analysis carried between conventional gate oxide, multi oxide an...

The paper illustrates the performance of Tri-Gate (TG) Dual Material (DM) SOI (Silicon on Insulator) Junctionless (JL) FET operating in Junction Accumulation Mode (JAM). An analytical model is developed to evaluate its performance. device also simulated using Silvaco simulator. Both and simulation results are compared found match closely. Quasi 3-D modeling approach adopted here determine surfa...