In this survey paper, a literature study on analytical delay models for a CMOS inverter and transmission gate has been done. Inverter followed by Transmission gate structure appears in many CMOS circuit design. Initially, the delay calculation of this entity is done considering them individually, which is not good. In this case, it does not account for the series stack effect that appears while...

In this paper, we show that both the global and local gate duplication problems for delay optimization are NP-complete under certain delay models.

One of the most notable features of nanometer scale CMOS technology is the increasing magnitude of variability of the key parameters affecting performance of integrated circuits [1]. Although scaling made controlling extrinsic variability more complex, nonetheless, the most profound reason for the future increase in parameter variability is that the technology is approaching the regime of funda...

One of the most notable features of nanometer scale CMOS technology is the increasing magnitude of variability of the key parameters affecting performance of integrated circuits [1]. Although scaling made controlling extrinsic variability more complex, nonetheless, the most profound reason for the future increase in parameter variability is that the technology is approaching the regime of funda...

Article history: Available online 17 February 2011 Keyword: Dynamic XOR/XNOR Gate Leakage Power Variation 0167-9317/$ see front matter 2011 Elsevier B.V. A doi:10.1016/j.mee.2011.02.068 ⇑ Corresponding author. Tel.: +86 15001166864. E-mail address: [email protected] (J. A hybrid network technique is proposed in dynamic CMOS XOR/XNOR gate to reduce the power consumption, save the layout...

One of the most notable features of nanometer scale CMOS technology is the increasing magnitude of variability of the key parameters affecting performance of integrated circuits [1]. Although scaling made controlling extrinsic variability more complex, nonetheless, the most profound reason for the future increase in parameter variability is that the technology is approaching the regime of funda...

In this paper, we propose and validate a novel design for a double-gate tunnel fi eld-effect transistor (DG Tunnel FET), for which the simulations show significant improvements compared with single-gate devices using an SiO2 gate dielectric. For the fi rst time, DG Tunnel FET devices, which are using a high-κ gate dielectric, are explored using realistic design parameters, showing an ON-current...

Airport gates are one of the congestion points of the air transportation system. When an arriving flight lands on a runway, it is possible that it cannot pull into its gate. We define this phenomenon as gate-waiting delay. This paper analyzes the degree to which gate waiting is a problem and the functional causes of gate waiting. Analysis of flight performance data for the OEP 35 airports for t...

This paper presents the design and implementation of a new digital-to-time converter (DTC). The obtained resolution is 1.02 ps, and the dynamic range is about 590 ns. The experimental results indicate that the measured differential nonlinearity (DNL) and integral nonlinearity (INL) are −0.17~+0.13 LSB and −0.35~+0.62 LSB, respectively. This DTC builds coarse and fine Vernier delay lines constru...