Considering multiple applications on a system which are executing concurrently, there should be mechanisms and policies which manage the competition for resources between them and resolve the conflicts. In a traditional system, these management activities can be summarized as storage management for saving the required data and I/O management to interact with the outside world. Theoretic foundat...

 Defragmentation is a fundamental resource management service allowing Reconfigurable Computing Systems (RCSs) to efficiently utilize resources when tasks are dispatched dynamically. Only well orchestrated interactions between the components of the reconfigurable resource management system can sustain the highest possible performance level for applications running on these RCSs. While scheduli...

This report briefly describes an ongoing research related to optimization of allocating software components to heterogeneous computing platform (which includes CPU, GPU and FPGA). Research goal is also presented, along with current hot topics of the research area, related research teams, and finally results and contribution of my research. It involves mathematical modelling which results in goa...

In this article we describe our experience and progress in accelerating an FPGA router. Placement and routing is undoubtly the most time-consuming process in automatic chip design or connguring pro-grammable logic devices as reconngurable computing elements. Our goal is to accelerate routing of FPGAs by 10 fold with a combination of workstation clusters and hardware acceleration. Coarse-grain p...

This paper proposes an effective fingerprint identification system with hardware block for thinning stage processing of a verification algorithm based on minutiae with 39% occupation of 32-bit RISC microprocessor cycle. Each step of a fingerprint algorithm is analyzed based on FPGA and ARMulator. This paper designs an effective hardware scheme for thinning stage processing using the Verilog-HDL...

Two important optimizations within the FPGA design process, C-slow retiming and datapath placement, offer significant benefits for designers. Many have advocated and implemented tools to use these techniques in both automatic and semiautomatic manner [1][2][5] but they have not made their way into conventional FPGA toolflo ws. C-slow retiming[3] is a method of accelerating computations that inc...

This paper presents a methodology for mapping linear processor arrays onto FPGA components. By taking advantage of regularity and locality properties of these structures, a placement is pre-deened, allowing vendor tools to skip this phase and produce fast and optimized routing. 1 Introduction In many compute intensive applications such as image or signal processing, time is mostly spent in exec...

this paper mainly focused on implementation of aes encryption and decryption standard aes-128. all the transformations of both encryption and decryption are simulated using an iterativedesign approach in order to minimize the hardware consumption. this method can make it avery low-complex architecture, especially in saving the hardware resource in implementing theaes inversesub bytes module and...