In floorplanning of very large scale integration design, it is useful if users are allowed to specify some placement constraints in the packing. One particular kind of placement constraints is to pack some modules on one of the four sides: on the left, on the right, at the bottom, or at the top of the final floorplan. These are called boundary constraints. In this paper, we enhanced a well-know...

-The strongest challenge that a VLSI designer has to face today is the extremely high heat generation within a chip which not only degrades the performance but also the yield and reliability are greatly affected. The situation even became worse with the evolution of multi-core processors with billions of devices in a single chip and due to die-to-die temperature variations within the chip. This...

We present a framework for the automatic generation of layouts of statechart diagrams. Statecharts [16] are widely used for the requirements specification of reactive systems. Our framework is based on several techniques that include hierarchical drawing, labeling, and floorplanning, designed to work in a cooperative environment. Therefore, the resulting drawings enjoy several important propert...

This paper presents a jfloorplanner for datapath with the capability of re-allocating data storage for minimizing the interconnect area and critical path delay without altering the number of Functional units and the schedule. The tool has combined two novel approaches: 1 A placement & Routing model to handle different architectural topologies (mux. and/ or bus based) suitable for FPGA's. 2 An e...

Temperature affects not only the performance but also the power, reliability, and cost of the embedded system. This paper proposes a temperature-aware task allocation and scheduling algorithm for MPSoC embedded systems. Thermal-aware heuristics are developed, and a temperature-aware floorplanning tool is used to reduce the peak temperature and achieve a thermally even distribution while meeting...

In this paper, we deal with arbitrarily shaped rectilinear module placement using the transitive closure graph (TCG) representation. The geometric meanings of modules are transparent to TCG as well as its induced operations, which makes TCG an ideal representation for floorplanning/placement with arbitrary rectilinear modules. We first partition a rectilinear module into a set of submodules and...

Modern three-dimensional (3D) designs, in which the active devices are placed in multiple layers using 3D integration technologies, are helping to maintain the validity of Moore’s law in today’s nano era. However, progress in commercial 3D ICs has been slow due to multiple reasons. One of them is the lack of appropriate physical design (layout) tools that take the new constraints arising from t...

This paper presents a set of techniques and a new design flow to be used in the synthesis of high-performance deep-submicron logic circuits. The design flow consists of circuit partitioning into tree-like clusters, floorplanning, global routing, and timing analysis/budgeting steps, followed by simultaneous technology mapping and linear placement of each cluster. The strength of this approach li...

With the proliferation of the transistor count in VLSI design, more and more design groups try to figure out an efficient way to combine their designs. The Internet features distributed computing and resource sharing. Consequently, a hierarchical design can adequately be solved in the Internet environment. In this paper, we demonstrate the facilitation of the Internet environment by solving the...