This paper presents results of a design that uses CMOS current mode logic that can be used to implement the high precision, speed critical elements of the mixed-signal systems. The design is based upon the 0.25-μm CMOS TSMC process. The propagation delays of the new current mode logic are compared to those of equivalent gates implemented in conventional CMOS logic. The results show a propagatio...

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In this paper, a new strategy of switchable CMOS phase-locked loop frequency synthesizer is proposed to increase its tuning range. The switchable PLL which integrates two phase-locked loops with different tuning frequencies are designed and fabricated in 0.5 μm n-well CMOS process. Cadence/Spectre simulations show that the frequency range of the switchable phased-locked loop is between 320 MHz ...

In CMOS multistage clock buffer design, the duty-cycle of clock is liable to be changed when the clock passes through several buffer stages. The pulse-width may be changed due to unbalance of the pand n-OS transistors in the long buffer. This paper describes a delay locked loop with double edge synchronization for use in a clock alignment process. Results of its SPICE simulation, that relate to...

There are a number of high volume applications for DC motors that require precision control of the motor’s speed. Phase locked loop techniques are well suited to provide this control by phase locking the motor to a stable and accurate reference frequency. In this paper, the small signal characteristics, and several large signal effects, of these loops are considered. Models are given for the lo...

DLL is used as a clock generator due to its stable operation and relatively simple design. Analog DLL has the advantages of lower phase offset and lower clock jitter than digital DLL. However, locking speed is slow in analog DLL. This paper proposes a dual edge triggered phase detector to enhance the locking speed of analog DLL and suggests a closed-form expression of locking speed which can co...

This paper proposes a low-power all-digital phase-locked loop (ADPLL) with calibration-free ring oscillator (RO)-based injection-locking time to digital converter (TDC) for BLE applications. The RO is reused as the delay cell of TDC, and quantization step TDC always tracked period; hence no calibration needed in this architecture. We adopt tuning lower bandwidth so decrease power consumption in...

A number of approaches to parametric estimation of signal phase are addressed. The goal is to estimate the phase, or more precisely, the parameters of the phase of a signal corrupted by white Gaussian noise. Signal models are restricted to those with linear and quadratic phase, but many of the results presented are applicable to signals with higher order phase laws. Results highlight the classi...

Lowand intermediate mass Higgs bosons decay preferably into fermion pairs. The one-loop electroweak corrections to the respective decay rates are dominated by a flavour-independent term of O(GFmt ). We calculate the two-loop gluon correction to this term. It turns out that this correction screens the leading high-mt behaviour of the one-loop result by roughly 10%. We also present the two-loop Q...