The buffer insertion has been a mechanism widely used to increase the performances of advanced VLSI digital circuits and systems. The driver or repeater used to this purpose has effect on the timing characteristics on the signal on the wire, as propagation delay, signal integrity, transition time, among others. The power concerns related to buffering have also received much attention, because o...

In a previous paper [3], one of the authors, gave a worst-case analysis for the Early Packet Discard (EPD) technique for maintaining packet integrity during overload in ATM switches. This analysis showed that to ensure 100% goodput during overload under worst-case conditions, requires a buffer with enough storage for one maximum length packet from every active virtual circuit. This paper refine...

Ion transport in control and streptozotocin-diabetic rat colon and ileum was studied using the Ussing chamber technique. No differences were observed between control and diabetic colonic mucosal short-circuit current under either basal or carbachol (100 nmol/L-1 micromol/L)-stimulated or prostaglandin E2 (100 nmol/L-1 micromol/L)-stimulated conditions. Similarly to colonic tissues, no differenc...

This paper deals with the high-speed switching operation of a main circuit when using silicon carbide (SiC) complementary metal-oxide semiconductor (CMOS) and power module for drive. When developed SiC CMOS gate buffer, we experimentally achieved turn-on turn-off speeds about -100 80 V/ns at DC bus voltage 600 V load current 20 A. Based on I-V characteristics charge MOSFET, approximate time was...

Along with the progress of VLSI technology delay buffers plays an increasingly critical role on affecting the circuit design and performance. This paper presents the design of a low power buffer. A gated clock ring counter is used to access the memory. The ring counter uses Double edge triggered flip flops instead of traditional flip flops to half the operating frequency. Also combinational ele...

Simple instrumentation amplifier circuit diagram using opamp. Equation The addition of input buffer stages makes it easy to match (impedance matching) the amplifier with the preceding stage. A single LM324 op amp Ic is a good choice. feedback differential amplifier. The LMH6550 has the an IF amplifier in high-performance communications. • Video Over TwistedSingle End to Differential Converter a...

A fully integrated pulsewidth modulator for Class-S power amplifiers is presented. It consists of a triangular signal generator, a comparator and output buffer. The HBT BiCMOS design of PWM circuit is applied to the LTE frequency range, which converts digitally modulated 955MHz RF carrier with 2.87GHz sampling clock. This PWM shows an EVM 6.6%, a differential output voltage swing 1.35Vp-p with ...

This paper reviews the modeling of subthreshold leakage current and proposes an estimation method for passtransistor logic circuit. The estimation method takes into account the subthreshold current at the output buffer as well as in the logic network, where only single offtransistors are responsible for the standby current during the steady state analysis. The proposed leakage model has been va...

IBIS (I/O Buffer Information Specification) is a standard that enables silicon vendors, simulation software and end customers to exchange modeling data electronic behavioral specifications of integrated circuit input/output analog characteristics. The intention this specify consistent format can be parsed by software, allowing vendors derive models compatible with their own products. reach exte...